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Comment by vitiral | Hacker News Reader

How do the chips not have clocks? I really like the design of the chips only communicating with neighbors.

I love GreenArray and everything about Chuck Moore and associates. I definitely think it can be taken too far though, FORTH could use some modernization. I'm making a language in it's spirit and also trying to think what a custom hardware solution would be GitHub.com/civboot/fngi.

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> How do the chips not have clocks?

That's a very good question. Asynchronous design is really cool, but has never gone anywhere that I know of.

https://authors.library.caltech.edu/43698/1/25YearsAgo.pdf

"One interesting experiment was using a hair dryer to heat up the chip. As the temperature rose, one could see the oscillation period stretch on the oscilloscope, and then shrink again as the dryer was removed"

In the old days there were some substantial asynchronous computers including the original (KA) PDP-10. I think the method is not used much these days. The GA144 is not really asynchronous. Each core is clocked by its own little ring oscillator, if I understand it right

I didn't know that about the KA PDP-10 nor had I looked that deeply into the GA144. Thanks.

The entire cpu itself _is_ the oscillator -- is one way to think of it. Calculating some boolean logic takes no clock, you just put the outputs on, and the outputs come out after some delay. If you connect 3 not gates in a ring, they will oscillate as the updated edge information propagates through each gate at some speed. Hopefully you see where this is going.

But if it takes more cycles to calculate the output than input it into the system, wouldn't you have a problem?

Others mentioned that they each have their own ring oscillator and that makes more sense. There is no _central_ clock, and each core has it's own memory. This also would mean there's no central bus. It's an intriguing design, I'm not totally sure I'm sold, but it definitely reduces some complexity.

If something stalls then everything else behind it stalls or stuff behind it diverts stuff elsewhere. There’s signals for the data being available and signals for being able to accept data and such things.

Is it possible to do this trick in a FPGA?

I would certainly hope so. FPGAs are also asynchronous (clock signals are optional, you can do pure discrete logic)

if you change forth in any way then it probably stops being forth. modern forth is factor or maybe even retro.

Right, hence why fngi is "in it's spirit."

Although... you can do anything in FORTH with sufficient knowledge of the interpreter, even write C syntax which gets compiled to forth-like words inline, so I'm not really sure what _isnt_ FORTH :)

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