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The entire cpu itself _is_ the oscillator -- is one way to think of it. Calculating some boolean logic takes no clock, you just put the outputs on, and the outputs come out after some delay. If you connect 3 not gates in a ring, they will oscillate as the updated edge information propagates through each gate at some speed. Hopefully you see where this is going.

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But if it takes more cycles to calculate the output than input it into the system, wouldn't you have a problem?

Others mentioned that they each have their own ring oscillator and that makes more sense. There is no _central_ clock, and each core has it's own memory. This also would mean there's no central bus. It's an intriguing design, I'm not totally sure I'm sold, but it definitely reduces some complexity.

If something stalls then everything else behind it stalls or stuff behind it diverts stuff elsewhere. There’s signals for the data being available and signals for being able to accept data and such things.

Is it possible to do this trick in a FPGA?

I would certainly hope so. FPGAs are also asynchronous (clock signals are optional, you can do pure discrete logic)

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