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Comment by 37ef_ced3 | Hacker News Reader

I attempted to port an AVX-512 neural net code generator (it produces stand-alone C code for, say, ResNet-50) to RISC-V vector instructions... but the conversion was unexpectedly complicated. Too time consuming, so I abandoned the project. The variable-width vector instructions are awkward.

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I checked https://NN-512.com and gituhb, trying to grok.

reading: https://gms.tf/riscv-vector.html

VLA (vector length agnostic) indirection makes the execution harder to control?

So... RISC-V does not provide instructions for each exponent

  MMX(64), SSE(128), AVX(256), AVX512(512)

and therefore the the compiler/assembler/human needs to use the input-length-agnostic instructions which the hardware lowers to operations that are implementation specific?

Thanks. Yes. Let me give you an example of the difficulties: The NN-512 code generator knows (with AVX-512) it can do an efficient (up to) 16x16 transpose, and makes heavy use of lane permutations. But with RISC-V vector instructions, you don't have that knowledge and you can't do the lane permutations efficiently.

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