Comment by palish | Hacker News Reader

Comment by palish | Hacker News Reader

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I think... Maybe... I'm getting it. Kind of. Probably not.

By wiring the CPU directly to the RAM, to use your metaphor, then we can entirely bypass the ASM stage of "a program" (but then what is a program if not a sequence of instructions?) and therefore we may better predict which data our program needs at runtime? Thereby caching that data more effectively than the random access patterns of Von Neumann?

Basically, instead of "accessing a pointer causes its data to be cached into L1", it would be... Well, I have no idea. Something else?

Here are my points of confusion, sorry:

1) in this non-Neumann paradigm, there will still be "data", in the traditional sense, right? (Or is "everything a program"?)

2) then... There will surely still be "caches" for that data, yeah? (Or is that what I'm missing? But without caches, I don't understand how it could be faster.)

But yeah, I don't want to waste anyone's time... certainly not anyone of your guys' caliber. Don't feel compelled/obligated to reply or anything. :)

Nope, still missing it.

When you wire the RAM to the CPU you don't need a cache. Imagine you have a billion or even a trillion registers, or more. That's a non-Von Neumann architecture. You're not shuffling data around on buses, the data is directly connected to the CPU.

Look at the example I gave again. Consider a simple addition command. The first CPU instruction says "take the word at this memory address, and move it to a register", the second does the same with a different address, the third adds the two values in the registers, the fourth then puts the result back in some other memory location. But what if there's no difference between the memory and registers? Instead you just have one instruction that says: add the values at these two locations, put the result at this other location. Now you've replaced 4 clock ticks with one clock tick. More than that, you save however many clock ticks it would have taken on average for the data to get to / from main memory (sometimes cached, sometimes not). Such an architecture would mean that you only have to wait on things you really have to wait on, like network and device latency, etc.

The structure of programs need not be terribly different per say, it can still be a sequence of instructions in memory. There are other non-Von Neumann architectures which would work differently (such as neural networks), but those are even more complicated.

Except addressing that amount of memory is still going to need a bus, it doesn't matter if the memory is sitting right on top of the CPU core or in the next room. It simply isn't going to be possible to provide direct access to every single memory cell when there are billions of them. This is still going to be a von Neumann (actually Modified Harvard) architecture, it's just going to be blazingly fast.

Now, once we start applying memristor implicational logic data processing we will have truely left the confines of the von Neumann architecture.

Don't need a cache? The larger your memory is, the greater the access latency will be, even if it's directly on the CPU die. That's why L1 and L2 caches tend to be around 32*2 and 256 KB, respectively. Most of the cache access time comes from the wire delays of sending signals around, and the larger the cache is, the longer the wire delays will be.

If you have a bunch of memory directly on the CPU, caching will still give significant speedups.

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