Looks like you want to implement "asynchronous circuit": https://en.wikipedia.org/wiki/Asynchronous_circuit
These basically need a handshaking logic for every independent data path.
These basically need a handshaking logic for every independent data path.
To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to circuit design as technically what you're doing is configuring them) For us an instruction on a CPU is a sequence of many smaller events, sometimes happening in parallel, which all need to be properly ordered to get a correct result. The most basic example is adding two multi-bit numbers, as was given in tremon's earlier comment, how does the next circuit know that all the bits in the result are ready to be consumed? To us those are parallel processes too, and we synchronize them. Sometimes by design (i.e. this process is guaranteed to complete before the next tick) and sometimes with a separate handshaking circuit. But no matter what, there is always some form of synchronization present in the machine itself.
If not, I don't know of a way to make that machine without some timing assumptions. https://authors.library.caltech.edu/26721/2/postscript.pdf
Maybe other people do though...
That's the point to asynchronous flowchart programming. Everything is event driven unless timing is specifically specified on the flowchart and synchronization takes place on the flowchart. Flowcharts do not represent the flow of time they represent the flow of events. Timing closure then becomes ensuring that every atomic path on every flowchart meets a system throughput requirement. The flowcharts are partially ordered according to an algorithm that follows the flowchart lines and therefore ensures that these partial orders (atomic path's) are pipelined.