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Comment by TheOtherHobbes | Hacker News Reader

The problems are power consumption, speed, cost, size, development time, and the difficulty of updates and bug fixes. A modern embedded processor handily solves all of those.

Boards full of TTL are a fascinating engineering exercise, but there aren't many applications where they're a better solution.

It's also tempting to cheat and solve some of the sub-problems with monostables and analog timers. As soon as you do that you're introducing potential issues caused by temperature drift, component tolerances, and component ageing.

A fully clocked solution is always more reliable, but often that means a higher component count and cost.

FPGAs have real applications, but they're still harder to develop than code.

When I was a student one of the tutors said "We'll all be doing this in software soon" - and he was right.

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"difficulty of updates and bug fixes"

We as EE engineers learned to test our creations. We are however slowly pushed to a SW process world where there are modules and integration tests and at the end, testing is just pingponged between EE and System and nobody do the testing.

> power consumption

That's the only one I don't quite understand. All your other points are definitely great objections.

Are you saying that a clocked system consistently uses less power than a stateful but quiescently 'static' circuit? I can imagine there's a reason, but it goes counter to my experience that the faster you clock a microprocessor the more power it consumes; therefore at zero clock rate a purely data-driven system should consume the least power. What am I missing?

Roughly, the power of a digital system is sum of the static power and the dynamic power (P=1/2 CV^2*F).

1. Discrete logic chips tend to be built in substantially larger process nodes (microns vs nanometers) that are less efficient. This means higher leakage current and more static power.

2. Discrete logic has to drive traces on a PCB, which have substantially higher capacitance (C) and therefore use more power getting across a board.

3. Discrete logic operates at higher voltages. Contrast 5V TTL vs. 1V core voltage inside a processor. Power is proportional to the voltage squared.

4. A microprocessor running even at low speed can replace a massive number of discrete logic chips, so for simple solutions F is low. If you're doing something very simple and interrupt-driven, F can be in the tens-hundreds of kHz.

Consequently, there's a whole lot more of both static and dynamic power with discrete logic than with a uC.

False. CMOS gates (4000-series) consume no power except when they switch. And they work at low voltage.

There are ways to make a microcontroller use less power, by making it hard-sleep when nothing is happening, but you don't get that without extra work.

Appreciate that description. Helps crystalize exactly how revolutionary microprocessors were compared to other contemporary approaches.

I don’t understand speed, either. Once you have the desired circuit, you don’t have to build it out of discrete components, you also can send it to a fab (I think that already happened with 7400-style ICs, too. The 74248 BCD to seven segment decoder doesn’t contain lots of individual NAND gates)

That will introduce practical problems, though. If you want your design on the best tech possible, that costs serious money that you may not be able to afford, especially if you don’t want an enormous number of circuits. Your 10,000 transistor design may fit a million or more times on a top-of-the-line die.

> Once you have the desired circuit, you don’t have to build it out of discrete components, you also can send it to a fab

You are still going to use a very old and obsolete process, compared to the microcontroller.

As a rule of thumb, every generation of lithography that has made transistors smaller and more efficient, has also roughly doubled the NRE costs. As you move down the feature size slope, you get all kinds of useful properties, but the tradeoff is that you have to manufacture more of any given design for it to be able to make any economic sense. To the point where you can get an amazing chip that has an arm core, storage and memory in a single package that costs pennies (well, not right now it doesn't, but it did in the past and will again) and uses almost no power, so long as you can use the exact same device that is also shipped in the millions for other things too.

Cost of fabbing an ASIC is 7 figures. Cost of compiling software is approximately zero. This is assuming that the development costs are similar.

Simplest explanation, that universal logic chips MUST have very wide tolerances, to be really universal.

- They have to use significantly higher voltages and consider higher currents, than really need to work.

For example, typical logic output of universal TTL logic, considers connect to it more than 10 inputs, each of them drain some current.

And also, universal logic i/o MUST tolerate some differences in power supply voltages and interference on real circuits.

But if you don't need to communicate to outside of chip, you could make things much more optimized, make customized outputs, considering for only as much drain as really exists in scheme; make internal highly stabilized power supply and very powerful power distribution network.

For first CPUs this was not talked, they just considered as very expensive logic chip, but ~ from 80186, hard to say exactly date, appears division: some outputs become high power, others stay "normal", low power.

And in commodity cpus, in Pentium appear two voltages - one for core and other for interface circuits.

I could not disagree more. These were highly reliable and effective systems long after their expected design lifetime. The F14 CADC is one example, as well as earlier ADC's.

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