> It's clearly a Core derivative with a uop cache, if you look at the overall structure of the pipeline.

Er, no. The structure of the pipeline is exactly what it took from the P4. P6 derivatives, including core, store in-flight results in the ROB, and then write them back to the RRF at retire. RRF read ports are a limited, shared resource, with full throughput only achieved when most instructions get their operands from the ROB.

P4 and SNB store only pointers in the ROB, putting all results directly into the PRF, with no work done on retire. The PRF has enough ports to serve all requests. This is an entirely different way to organize the cpu.