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Comment by nwiswell | Hacker News Reader

Just so everyone is aware, terms like "2 nm" are industry jargon used primarily for marketing and roadmap comparisons of process nodes. It doesn't really have any physical bearing on the sizes of the devices involved anymore.

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I hear this statement quite often, but never paired with what numbers we should be using. Are there any? Do we know anything about these fabs that is worthwhile to make a comparison?

Like any sufficiently complex thing, it takes a lot of numbers to create a representative profile.

One somewhat useful figure you’ll see used is MTr/mm^2 or mega-transistor per square millimeter. That number can change depending on what exactly those transistors are being used for (which cell libraries are used).

IIRC Intel proposed a standard ratio for such measurements a while back.

Density doesn’t make a process better for everything however.

Useful measurements are particularly difficult when trade-offs are inherent options.

For memory: space, speed, power required, longevity (against time, against temperature / ambient energy).

Computation usually requires some tiny bits of very volatile memory (registers, cache, invisible buffers, etc), but similarly must have tradeoffs for space, speed, power, and longevity.

Radiation Hardened / hostile environment design libraries can also be useful for automotive, heavy industry, military, and space hardened applications. I'm not sure of the details but guess they'd frequently use more space, power, and possibly even active shielding (E.G. additional layers of conductors and/or capacitors sandwiching the logic bits to try to protect them and stabilize local currents).

Radiation hardening is commonly done by triplicating everything, and taking/resyncing the majority result.

(At least for FPGA-based satellites. I'm sure there are many varied approaches at play these days.)

I think its quite known now that its industry jargon, but when did they start doing that as I presume it wasn't always the case.

Up until 45nm the name of a process node was twice the length of a transistor's gate. At that point it stopped being technologically feasible to reduce the gate length but companies were able to find other ways, such as fin FETs, to pack ever more transistors in with each node without having to reduce the transistor length.

This is not correct. First, process node names were the same as the minimum transistor gate length, not 2X. Second, at least down to 28nm, this relationship held true. It may have also been the case for 22nm. It all went out the window with finfet processes.

When they changed from planar transistors to more 3D-like transistors like FinFET, I believe. I'm pretty sure 55nm and probably 28nm still has minimum pitch of that size.

Problem was that people had certain expectation that a "45nm" process could fit more transistors than "90nm" one. Would be kind of awkward to name it like "22nm++++" and you have no idea roughly how much better it was than the old planar "22nm" process.

I don't think it was any one time, just a slow drift away from Moore's law physically while the marketing department followed it strictly (as well as defined the nodes before the processes were actually developed, so they were going off best guess).

I still read about claims that Moore's law is ending due to quantum tunneling because the transistors are getting too tiny.

What is Moore's law up to these days? I feel like that, as a user, nothing got faster for about a decade between 2010 and 2020 (not quite right, more like 2012-2018). Instead everyone was like "oh it requires less air conditioners in a data center!" or "uh we're out of ideas, have 32 cores". OK, but I need more FPS from my game. I have a great air conditioner.

That seems to have changed in the last couple years, though. AMD and Apple seem to have gotten serious.

(I know, Moore's law is about transistor count, and I guess adding more cores technically increases the transistor count. But as a software engineer, I need my chips to get 2x faster every 18 months, or I'll have to start using a profiler or something!)

It used to be that when you shrank a transitor you would be able increase clock speeds by default thanks to something called Dennard scaling. That stopped happening in the mid 2000s. Price per transistor, transistor density, and energy efficiency are all continuing to get better exponentially but new semiconductor plants are also going up in price exponentially so more and more companies are dropping out of the race. You can look at the Wikichip page to see how much attrition there's been.

https://en.wikichip.org/wiki/technology_node

I upgraded from Ivy Bridge to a Ryzen 2700, the difference is extreme. One of those could barely encode a 1080p stream in real time the other one can encode at least eight and probably 16 but I never needed that many.

Hey, performance tuning is fun! You should try it.

With finFETs the transistors are not physically getting smaller anymore. Instead, by making taller and taller finFETs, you can squeeze the transistors closer without actually having smaller transistors. By some definitions, you can say Moore’s Law is already over, or at least no long operates via the traditional methods.

It's "quite known" if you already know it. I didn't.

I suspect it started when engineers stopped making the important decisions and people with merely a business background took over.

What would be next? 1nm and then 0nm? They're about to run out so I suspect they need a new marketing/roadmap naming convention

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