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I wonder how soon we will have microarchitectures that are purely the result of some deep learning algorithms optimizing for performance and compilability of high level languages. We would be able to prove them correct - that they correctly execute the code and have no exploitable bugs - but we will have almost no idea how exactly they achieve said performance.

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I can’t find the link atm, but the reference was a self-optimized circuit that achieved xyz objective but the actual fpga bitstream was a p&r nightmare of latches and impossible simplifications taking advantage of phantom this and inductive that all accidentally and due to proximity but measured results and feedback and such. Totally specific and local, down to clock skew usage, whatever, no one understood it… will have to find the link…

That sounds about right. Why bother with a clock anyway, asynchronous is the way of the hardware samurai.

Although it should be fuzzed a bit with signal and power noise, to kill those "solutions" that only work due to a lucky photo-resist error that manifests itself at exactly 3.03V.

I don't think we really know how to learn code generation techniques and prove them correct, yet. That would be, in general, a really neat and useful trick.

What, divide in half and compare?

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