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Comment by proto_lambda | Hacker News Reader

Fast Ethernet is better than no Ethernet, and gigabit is unachievable in low-end FPGAs.

But if you have IO fast enough to do direct 100Mbps Ethernet, you can do GMII or RGMII to a gigabit PHY (or a parallel to serial converter to talk to an SFP). I think the project here goes through MII internally anyway (I only skimmed it) so it would actually take more space on the FPGA fabric than using a PHY…

So apart from being fun, maybe the main benefit would be less board space because it doesn’t need the PHY chip? (But also potentially lots of disadvantages practically).

Yeah. A Fast Ethernet PHY that does 10/100 Ethernet with auto-negotiation, auto-MDI/MDIX etc. is less than $1 in quantity and fits in a footprint a couple of mm on each side.

I think this is a "because I can" sort of thing.

GigE not being achievable on low-end FPGAs explains it really well, thank you.

RGMII only requires a 125MHz clock; which is not particularly fast. It depends what you mean by "low-end", but you can certainly implement gigabit Ethernet on something like an Intel/Altera MAX 10 for example. It does rather depend on what you want to do with it though.

20 Euro Colorlight 5A FPGA boards from Aliexpress come with dual Gigabit Ethernet ports, open toolchain to build a SoC that can access them as well.

LiteX allows me to use it as a Gigabit Ethernet powered logic analyzer with a lot of inputs.

No, if the FPGA can do this, then it would be perfectly capable of interfacing to a gigabit PHY or a parallel/serial converter for a Gigabit SFP.

At the moment I have Artix 7 with ancient gigabit PHY running GigE. In Xilinx eco-system it is pretty low-end device.

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