I wonder, which instruction fusions are implemented, as it is key to high-performance RISC-V and the reason not to have conditional movs & alike in macro-ISA.
Unfortunately, documentation for Micro-ISA is in Chinese only :-(
Unfortunately, documentation for Micro-ISA is in Chinese only :-(
Fwiw, this is the relevant link: https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/d...
https://raw.githubusercontent.com/riscv/riscv-bitmanip/maste...
If you do instruction fusion, you might be able to transform the typical pairs that would create a short branch and simply convert them into a cmov micro-instruction. That it does not make the branch predictor much more complex.
The ternary instructions didn't pass the test for utility vs cost and were not ratified.
For example `cmix` only replaces three other instructions, two of which can be done in parallel. Emulating `cmov` is slightly more expensive: generate an all-1s or all-0s mask from your condition (e.g. `slt mask,a,b; neg mask,mask` and then do a `cmix`.
Applications that want `cmov` for constant execution time for security reasons can cope with it using a couple of extra instructions. Applications that want `cmov` for average performance because the condition is unpredictable are mostly mistaken with modern branch prediction :-)
There is a fairly strong possibility that a pair of instructions might be added to put `cmov` emulation on the same footing as `cmix`:
Rd = Rs2 ? Rs1 : 0
Rd = Rs2 ? 0 : Rs1
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...
The specs themselves come with a lot of rationale for decisions taken.
But, as a starting point (from zero), I recommend the "RISC-V Reader" book, by the main authors of the ISA, as it makes a great introduction to the design of RISC-V.