When you sell to Rich Arabs the rule is to follow the yatch salesman playbook. The main goal is to get an arms race going among them. An nytimes article (usually framed and displayed prominently) seeds the process.

> Having such a large processor means the data never has to go off-die and wait in memory, wasting power, and can continually be moved onto the next stage of the calculation in a pipelined fashion. The compiler and processor are also designed with sparsity in mind, allowing high utilization regardless of batch size, or can enable parameter search algorithms to run simultaneously.

https://www.anandtech.com/show/16626/cerebras-unveils-wafer-...

Ok not affiliated with Cerebras, but generally speaking I believe the idea is that since you're making a big wafer with all your cores the data transport latency for going core to core (much less core to memory/memory bus to gpu memory) is much lower.

From first principles there's gains to be had but I suspect "other things" bottleneck performance. Could be wrong though. I would find it hard to believe if absolutely no models were data latency constrained.

Try this keyword: "anandtech cerebras". You'll find a lot of details.

The basic premise is that data does not have to move off a giant chip as often as a normal sized chip.

They don't even tell us how fast they are, are they?