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Comment by _chris_ | Hacker News Reader

I believe early on there was a change to a pre-AUIPC instruction due to potential infringement fears (for PC-relative indexing); but everything else was understood to be following well-worn paths.

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Interesting. I hadn't heard that, but then I was a late-comer in 2016 with the user ISA already in its current form. I have some vague memory of having seen something about RISC-V a few years earlier than that, and glancing at the ISA, and not being impressed. But by the time the HiFive1 came it all looked pretty great to me. Not perfect — `SLT[I][U]` should produce 0 or -1 not 0 or 1, for example — but pretty darn good. The C extension also made it vastly more attractive as a practical ISA, and that was a late-comer (even if always "planned" and already mentioned as being developed in the May 2011 spec).

Looking at the May 2011 spec (https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...) there is `RDNPC Rd` which simply loads next PC into Rd. So that's 4 bytes different to modern `AUIPC Rd,0`, and functionally identical (other than return address predictor SNAFU) to modern `JAL Rd,.+4` or 2011 `JAL .+4` (only `x1` supported).

So 32 bit PC-relative addressing needed `RDNPC;LUI;ADD` and then `JALR`/load/store vs modern just `AUIPC` before the main instruction.

If there was something before `RDNPC` then it much have been very short-lived!

There is allegedly an earlier RISC-V design here...

https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris...

... but I get "You don't have permission to access this resource."

There is an updated 2011 version which appears to conform to the May 2011 spec. The instruction listing omits load/store byte/half and there is no relative addressing support at all (except `JAL 4`) but that is probably just simplification for a hardware design class.

https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/lab2-ris...

Chris, do you have access to that fa10 version?

I also get a permission error: but I think this (https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/lab2-ris...) is the same file, and functionally the same as the fa11 version?

I think RDNPC is what I was thinking of, but I can't at all remember what was perceived as "risky" about it. I may be overblowing something from memory. AUIPC is better anyways.

Ohh .. the ISA changed quite a bit between 2010 and May 2011!

- 2010 opcodes left justified like MIPS, 2011 right justified and a func3 like modern RISC-V .. but rd on the far left, not between func3 and opcode.

- register names in formats changed from xa, xb, xc (dst) to rs1, rs2, rd

- 2010 lw uses xa for dst, sw uses xa for src like MIPS, ARM etc. 2011 has rd always in the same place, with sw using rs2 not rd, like modern RISC-V.

- 2010 jalr has no offset, 2011 has 12 bit offset like now.

- 2010 the literals for ANDI, ORI, XORI are zero-extended, 2011 unspecified (so I think all sign-ext)

- 2010 j/jal have 27 bit offset (28 with shift?), 2011 25 bit field.

- 2010 ADD/SUB/shifts have *W suffixes. 2011 is is like modern RV32.

- 2010 has SRA / SRAI, 2011 only has logical. Possibly just a simplification for the lab.

If you want to do some further archeology, check out the SMIPS ISA, which I believe dates back to 2005 (which itself gradually evolved from the T0/Scale/6.371 MIPS ISAs; and the earliest, T0, was derived from MIPS-II).

Seems to be just exactly MIPS-II, down to the encoding, but with stuff left out.

http://csg.csail.mit.edu/6.S078/6_S078_2012_www/handouts/smi...

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