Comment by InclinedPlane | Hacker News Reader

Comment by InclinedPlane | Hacker News Reader

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He was "right" in that he made a prediction that did not come anywhere near true?

Sorry, he was wrong.

As to the 2nd point about x86 vs "RISC" processors, it turns out he was so massively wrong the very basis of his understanding was incorrect. CISC processors are dead today, they stopped being a substantial part of the market in the late 90s. I'm sure they still exist somewhere in new devices (RAD hardened Pentiums, perhaps) but for the most part the CISC vs RISC battle is over, and RISC won overwhelmingly. But Tannenbaum thought that a necessary consequence of that would be that the x86 architecture would die due to the weaknesses of CISC processor designs. But what actually happened is that Intel (and later AMD and others of course) started making processors with a RISC core that support the x86 (IA32) instruction set through transparent op-code translation. Every Intel cpu since the Pentium-Pro has worked that way (and every AMD CPU since the Athlon).

You can't just wave your hands and say "yeah, but he was fundamentally right in some ways though there were some things he couldn't have foreseen". That's part of the deal, there's always something that you can't foreseen. Imagining that CISC's weaknesses are identical to the weaknesses of the x86 architecture are just the sort of naivety and shallow reasoning that can lead you to make woefully wrong predictions.

Recently on a flight I sat next to a Ph.D. that ran a chip design consulting firm. In this fascinating discussion, he talked about the internal design of AMD and Intel processors and said exactly this. AMD and Intel haven't had hardware based x86 computation for a very long time.

Instead, they have a RISC style pipeline with an op-code translation layer that decodes instructions into smaller RISC-like instructions that get run through the pipeline.

So really, modern x86 processors are more like x86-compatible processors.

"CISC processors are dead today [...] Intel (and later AMD and others of course) started making processors with a RISC core that support the x86"

That's a pretty far fetched argument. RISC/CISC is about instruction set, and the x86 instruction set is CISC.

Of course since the big RISC/CISC battle the implementations have converged a lot on the microarchitecture level, primarily because the transistor budget sweet spot targeted by RISC melted away and the amount of chip area saved in instruction decode and ISA simplicity was later dwarfed by out-of-order machinery, caches etc.

So an equally valid argument (as "CISC is dead") is "RISC is dead" since RISC chips today have brainiac instructions and pipelines like divide/multiply, unaligned access, variable length instructions (Thumb on ARM), out-of-order execution etc.

That's sort of like saying that any RISC machine becomes a CISC machine at soon as you install the JVM on it (With the caveats that I don't know if the JVM has a CISC instruction set)

If all the end users use the CISC layer and no person uses the RISC layer, then I would feel comfortable calling it a CISC machine.

For those of you, like me, who are curious about the difference between RISC and CISC, here's a gentle introduction:

http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/pr...

Right. I think what Tannenbaum overlooked was the massive transistor budgets that were on their way thanks to Moore's law. Where early CISC chips had to spend a substantial fraction of their transistors on instruction decoding, the absolute number of transistors required for that didn't increase nearly as fast as the total on the chip. So now we have quite complex instruction decoders that translate CISC to RISC, and they're still just a small fraction of the chip.

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