Before making bold claims, it might be useful to get more familiar with a mess that are myriad of RISC-V extensions and seemingly insane/backwards decisions it makes completely ignoring the hard lessons learned by both ARM and x86.

Judging by the PC's history of transitioning from 32-bit to 64-bit x86 (still not complete after 20 years), and from x86 to ARM (Windows on ARM is at 14% market share after more than 10 years)… well. I'm just a bit skeptical.

Though to be fair, it all depends on the hardware. Windows on ARM struggled not just because it wasn't x86 but because nobody was making powerful-enough ARM processors. Now that those processors are starting to arrive, it's supposedly going to take off in the next few years. …Probably only on the low end, though. But you never know.

And RISC-V? Maybe someday.

For SIMD kernels that do "general-purpose computation" like formatting strings, parsing documents, or entropy encoding and decoding, it's difficult to use variable-length vector extensions, and ultimately these sorts of things written for these targets are likely to branch at runtime based on the actual width reported by the CPU. One of the most important operations for this sort of thing, TBLQ, doesn't even exist in SVE prior to SVE2.1 published ~1 year ago, so parser devs targeting aarch64 can safely target NEON until SVE2.1 lands in the hardware they care about.