If I read correctly, that concept maps really well to LUTs as used in FPGAs (but note it's not the same!).
Its author/inventor Mike Warot has the simple but useful idea of making the configuration space of such a device a simple memory array (like RAM or EEPROM cells). Write some bits to a memory location -> cell [x,y] in the device's grid is configured.
This would make it trivial to control/interface such a 'compute grid' to traditional cpus. To a cpu it would just look like regular RAM.
Anyone know if there's work towards applying that idea to FPGAs? It would basically evaporate the problem of [closed source FPGA vendor toolchains].
Obviously, bitstreams produced by FPGA vendor tools will do a somewhat similar thing. But what/how exactly is opaque. Not to mention encrypted bitstreams, read-protection & what have you. Hence require re-engineering effort for open source tool support.
Turning this into a dead simple 1:1 mapping would be a huge step forward.
I hope to learn enough Verilog/VHDL/RTL to take advantage of the Free Shuttle program they have[1] eventually.
Currently, I'm wondering how to go from expressions to code I can load into a bitgrid. The thought of parsing code, building an AST, converting that to an acyclic directed graph of binary expressions, to actual bits to load the grid with.... overwhelms me, and has me putting it off. 8(
I do have a working simulator, written in Pascal[2], that can run fairly quickly for toy problems on my desktop PC. So, there's been some progress.
I strongly suspect I can get there, but need an accountability buddy to push me along. I used to be a self starter, but I stayed in an IT Admin job too long that crushed it out of me.
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