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I like this approach (especially because it supports AVX-512), however even not counting the Zen 4c, AMD 3D v-cache CPU's have cores that are sufficiently heterogeneous (those with and without 3D cache) that some special scheduling is desired for some use cases (gaming on Windows)

Great video! Thanks for the link.

By the way, I was confused by how you equated architecture and RTL. In this context I use "architecture" to mean ISA. I use "microarchitecture" to refer to how e.g. its performance characteristics are realized, like IPC.

You seem to know more than I do and would love you to comment. Thanks!

Is that meaningfully different from Apple’s take?

I don’t think so. But it is different from some Intel CPUs where the efficiency cores didn’t support all the vector ops the performance cores did, causing issues with some software.