SiFive claims nearly A78 performance in half the die area. In wearables, this represents a lot of savings in area and probably in power consumption too. This is another move Apple might make as ISA backward-compatibility isn't very important in that market while cost and power are.
https://twitter.com/dylan522p/status/1415395415000817664
Great way to undermine your credibility.
A78 on SD845 used 64kb L1 vs 32kb L1 on P670 (a 32kb variant is available, but would get significantly worse performance relative to P670). Likewise, other things like the uop cache and 32-bit frontend add a lot to the size/power of A78 as ARM themselves bragged that their frontend got 75% smaller when they dropped the uop cache and 32-bit support in newer mid-core designs. I'd guess this frontend difference alone accounts for most of the area difference between the two.
If you have a super embedded system where your clock speed is tied to your memory frequency in a way where that's the limiting factor then performance/frequency can be a useful metic, but not in any system with caches.
But in all seriousness, I think RISC-V takes over the low- and mid-segments of embedded, industrial and maybe automotive SoCs