Actually thats why we need an AI to generate Verilog / VHDL from images of tomography so it can be testable part by part or whole on a FPGA or simulation.

Many part of the chip is actually replication of same compenent or library like DRAM, ROM, Arithmetic operations so always there should be a pattern. Scanning should also work from low resolution to high resolution part by part to find pattern.

And also foundry is not as much as you think, most of the cost is R&D not the production.

https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-... https://www.tomshardware.com/news/tsmc-reportedly-adds-advan...

"60-ish A100/H100 GPUs per wafer" and 7nm Waffer cost is $10k