I think it's "secret" because nobody really cares.
Do you care for example how the CPU maps the linear memory space across physical RAM sticks and chips? I recently discovered that there multiple alternatives and BIOS settings which give you some control over this.
You can't cheat physics, so at today's CPU speeds, spinning disk HDDs more closely resemble tape drives than not. You have to pay a significant performance price when moving the read head across the disk surface, moreso when you have to wait an entire rotation for the correct sector to fly under the read head.
Yet you want to store as much good data on the whole disk as possible, and need to be able to retrieve smallish chunks of the data back in the typical case quickish.
In turn, that constrains how you group data, and how you allocate ECC bits. As a seller of disks, it's probably how you decide if you should stick a 3TB, 4TB or 5TB sticker on the box too.
The end result will be an algorithm that, based on factory calibration and recent measurements decides how to map data to physical areas of the disk. One head giving a weaker signal lately? Well we're gonna assign fewer data bits there.
And when reading data back there are also decisions to be made. For example, when we read a bunch of data but the ECC recovery fails due to too much noise, should we re-read the same data and combine the reads to get more signal and less noise? Should we shake the head a little and see if we can re-read and get better alignment next time? Should we go and read a few tens of megabytes of other data and see if we can recover the data from a higher hierarchical level ECC/erasure coding scheme?
Wouldn't that cause all sorts of issues with SMR drives?
In addition, the heads have multiple levels of independent actuation beyond the shared arm itself[1][2].
So as long as the tracks themselves are fairly consistent, I don't see why the number of sectors per track has to be equal.
[1]: https://pcper.com/2009/09/wd-unleashes-nested-actuator-and-a...