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lazide

There is likely nothing 1nm in this 1nm process.

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What do you mean?

Exactly what he said.

It’s a marketing number and has been for many years.

They could at least use a number that would reflect the current transistor density if they could have that number of nm with planar 1980's transistors.

It does reflect transistor density. You can check this yourself:

https://en.wikipedia.org/wiki/Transistor_count#Microprocesso...

Back in 2019 Intel suggested the industry do this: https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-...

But nm size is so baked into culture, it didn't take off.

TSMC now labels their process e.g. “N3”. So there has been a shift away from nm in some contexts.

But it really doesn’t matter. There’s not a single physical number you can extract from the process that accurately describes its performance. So just continuing to use “nm” and assigning some number that feels right is actually a reasonable approach.

It used to be MHz and GHz, then when that stalled, advertising nm became a thing. It can change.

Angstrom is kind of a fun word, so I’m sure a few nodes will be named after that.

Transistor density for just, like, a grid of unconnected transistors? Or some reference design or something like that?

IMO it is interesting to get a general idea of where the companies are, but in the end the element size doesn’t matter to end users. People should check the linpack benchmarks of the chips that come out, or whatever.

SRAM size has not been scaling at all in recent nodes, so these days the notion of uniform scaling is also breaking down quite a bit. This means that future designs will have less cache memory per core, unless they use chiplets to add more memory (either SRAM or eDRAM) close enough to the chip to become usable as some kind of bespoke cache.

Just for the record, the "not at all" part is incorrect for the nodes I'm aware of. Correct would be "way worse", i.e. it's still getting denser, but the improvement is way worse than that of random logic.

TSMC's N3E (their first 3nm that will actually see broad use) has the same SRAM cell size as N5. Their original 3nm had 5% smaller SRAM cell size than N5, but that turned out to be too aggressive and the process was too expensive for most of their customers. So for the time being, TSMC has indeed hit a wall for SRAM scaling. But it looks like N3P will be able to shrink SRAM again.

Hopefully we can get really widespread 2.5D packaging and just start including “oops all SRAM” layers.

Thanks, I had missed that development.

That's what it is.

It has nothing to do with transistor density, and hasn't for twenty years.

I know, but it could be nice if it were.

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