> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks.

I say this as an FPGA engineer that started my career in software: This used to be the case in software too. But we now have such good tools with REPLs, automatic tests, IDE integrations, partial implementation possibility that it's simply way less inefficient to build software like that.

I feel like that is precisely where the current hardware ecosystem stands. VHDL/Verilog/SV are simply not good enough to use it as a design exploration tool.

Instead of saying: "We use HDLs just to put in the design which we do beforehand" it should be "HDLs are the central tool in digital design. Both during design exploration and implementation". I think this is what people want out of these "neo" HDLs. The way you are viewing it is as only as a straightforward drop-in replacement. That is not what it's about.