It is not certain if what AMD writes there is true, because it is almost impossible to determine by testing whether the 2 halves of a 512-bit instruction are executed sequentially in 2 clock cycles of the same execution unit or they are executed in the same clock cycle in 2 execution units.
Some people have attempted to test this claim of AMD by measuring instruction latencies. The results have not been clear, but they tended to support that this AMD claim is false.
Regardless whether this AMD claim is true or false, this does not change anything for the end user.
For any relevant 512-bit instruction, there are 2 or 4 available execution units. The 512-bit instructions are split into 2 x 256-bit micro-operations, and then either 4 or 2 such micro-operations are issued simultaneously, corresponding to the total datapath width of 1024 bits, or to the partial datapath width available for a few instructions, e.g. FMUL and FMA, resulting in a throughput of 1024 bits of results per clock cycle for most instructions (512 bits for FMA/FMUL), the same as for any Intel CPU supporting AVX-512 (with the exception of FMA/FMUL, where the throughput matches only the cheaper Xeon SKUs).
The throughput would be the same, i.e. of 1024 bits per cycle, regardless if what AMD said is true, i.e. that when executing 8 x 256-bit micro-operations in 2 clock cycles, the pair of micro-operations executed in the same execution unit comes from a single instruction, or if the claim is false and the pair of micro-operations executed in the same execution unit comes from 2 distinct instructions.
The throughput depends only on the total datapath width of 1024 bits and it does not depend on the details of the order in which the micro-operations are issued to the execution units.
The fact that one execution unit has a data path of 256 bits is irrelevant for the throughput of a CPU. Only the total datapath width matter.
For instance, an ARM Cortex-X4 CPU core has the datapath width for a single execution unit of only 128 bits. That does not mean that it is slower than a consumer Intel CPU core that supports only AVX, which has a datapath width for a single execution unit of 256 bits.
In fact both CPU cores have the same vector FMA throughput, because they have the same total datapath width for FMA instructions of 512 bits, i.e. 4 x 128 bits for Cortex-X4 and 2 x 256 bits for a consumer Intel P-core, e.g. Raptor Cove.
It is not enough to read the documentation if you do not think about what you read, to assess whether it is correct or not.
Technical documentation is not usually written by the engineers that have designed the device, so it frequently contains errors when the technical writer has not understood what the designers have said, or the writer has attempted to synthesize or simplify the information, but that has resulted in a changed meaning.