nope. Fab models are extremely accurate for mature nodes (like anything down to 3nm now). They keep updating after qualification runs, but you see they converge within 1-2 years. Even failure modes and probabilities are modelled extremely accurately

This is if you run full electrical circuit simulation. For complex digital chips you can't do that due to insane compute requirements. There comes in modeling and yield estimation wizardry in. But if you want to simulate the hell out of a reasonably small circuit (< 100M nodes), you can do that extremely accurately.