I doubt that you could use NAND Flash as RAM substitute as it is right now. Basically it's a block device with page size about 8KB and erase block ~ 2MB. Data could be read and written only in pages, in-chip page load times are on the order of 100us, page write 1ms, block erase -- 5ms, and it takes about 100us to transfer page data in either direction. So, random read/write latencies are 10^2 / 10^1 times lower than HDD's, but still about 10^3 / 10^4 times larger than DRAM's. I guess internal architecture could be redisigned to reduce block sizes and allow parallel operations inside a sigle chip, but it's unclear how much it will affect density and price.

But it would be useful to put NAND controller closer to CPU, remove block device emulation layer and let OS do wear-leveling and block allocation. We could get high-performance swap or put there specialized MTD filesystems like UBIFS.