I'm glad someone else thinks so!
There's a very interesting vid about the design of the ISA here https://www.youtube.com/watch?v=C53tGHzp1PI and I think it's pretty clear they learned from early MIPS/Sparc. It's a shame it got abandoned in the Itanium push.
The Alpha was also a performance king in that era, but tbh I don't have the same nostalgia for it, although clearly it was executed very well.
I think an updated PA-RISC design be awesome for modern workloads; huge caches with prefetch, a good branch predictor + a 8-10 wide dispatch, and some sort of vector extension. A Mix of AMD Zen+X3D & Apple ARM. To be fair, ISA doesn't matter as much really these days, any core with similar features probably would perform well.
There's always someone who thinks VLIW or a similar is a good idea. So far that's been a bit tricky for a general purpose CPU, or even some parallel designs.
* 100% personal opinion, I've never actually worked on HW design directly *