That is less than 4 of the 32 software-visible vector registers of an AMD Zen 4 or Zen 5 CPU, or of the future Intel CPUs that will reintroduce AVX-512.

There is no difficulty in defining AVX-512 instructions that would operate on a hash state of this size.

The real amount of 64-bit registers in a modern CPU is well above one thousand and the implementation of the SHA-3 functions is very efficient in hardware, so adding instructions for these hashes would have a very modest cost.

Keccak is core to the SHA3 standard. If speed is a concern, there are hand tuned assembly versions and hardware implementations out there.