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That reminds me a lot of the xmos xcore mcus with 8 cores. I am curious what kind of synchronization primitives have you added and why?

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I'm actually working on a comprehensive write up on exactly this topic that should be out sometime next week!

Just ordered 2 to play with!

thank you~~

Sounds like the Parallax Propeller 1/2 as well.

It's a good model for MCU stuff. There were people pushing Chip Gracey (Parallax) to use RISC-V instead of his custom ISA when he designed the P2 a few years ago, but he chose to do his own thing. Which has made compiler development difficult.

This seems more on the RPI side rather than propeller, propeller was never a really good choice for production integration. This looks like it could hold its own in many contexts.

If I understand the architecture it's both -- a main MPU style core and then a bunch of PicoRiscV cores doing MCU tasks. The smart thing about using RISC-V here being having a unified ISA so you can compile programs that run on both or move between both, etc.

I'm assuming he probably has some sort of roundrobin shared memory access similar to what Chip did with "HUB Ram" on the P2.

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