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Some more questions because the website isn't clear:
- does the FPGA handle digital beamforming in the FPGA fabric? or it controls RF phase shifters for analog beamforming?
- will we have access to FPGA pin constraint file so we can write our own verilog
- can I get IQ samples from the antenna elements and run my own beamforming algorithm / calibration in a separate PC with possible GPU acceleration? or it will be bottlenecked by rpi5 gigabit ethernet?
For IQ samples, you can stream a continuous 60 MSPS IQ beam over the Ethernet, but for custom beamforming algorithms, the processing needs to be distributed across the FPGAs (for MoonRF it is a SERDES daisy chain, using the same FFC connectors as the links to the RPi-5).
Yes I'll put some newer block diagrams on the website this week. Thanks for the reminder.