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Comment by forinti | Hacker News Reader

I was thinking lately about how much memory you could handle on a 6502. The BBC Micro had a 16KB block of RAM paged between up to 16 ROMs/RAM but if you could have 256 banks you could do 4MB. One problem is that that would require a very large PCB. Another problem is that the OS searches for commands on all the ROMs and this would become slow for so many banks; one solution would be to limit the ROMs to the first few banks and let the rest be RAM.

It could be useful for some sort of minicomputer for business applications.

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The Commodore REU (RAM Expansion Unit) architecture for the C64/C128 allows for up to 16 MiB - 256 banks of 256 addresses in 256 pages.

Due to the lack of support hardware in the C64 (no hardware RAM bank switching/MMU) this memory is not bank switched and then directly addressable by the CPU, it's copied on request by DMA into actual system RAM. But in some sense, a C64 with a 16 MiB REU is a 6502 with 16 MiB RAM.

But yeah, you want CPU addressable RAM with real bank switching. You couldn't really do 16 MiB, you wouldn't want to bank switch the entire 64 KiB memory space. The Commander X16 (a modern hobbyist 6502 computer) supports up to 2 MiB by having hardware capable of switching 256 banks into an 8 KiB window (2 MiB/256 banks = 8 KiB).

Let's say you design something with 32 KiB pages instead -- that seems kind of plausible, depending on what the system does -- you could then do 256*32 = 8 MiB and still have 32 KiB of non-paged memory space available. I think this looks like just about the maximum you would want to do without the code or hardware getting too hairy.

Depends entirely on what banking scheme you use. Nothing stops you from adding e.g. an 8-bit banking register (even two of them, one for instruction fetches, another one for normal memory reads/writes) to serve as bits 23–16 for the 24-bit memory bus. That's what WDC 65C816 from 1985 does, but it also goes full 16-bit mode as well.

And if you have a 16-bit CPU, you can do all kinds of silly stuff; for instance, you can have 4 16-bit MSRs, let's call them BANK0–BANK3, that would be selected by the two upper bits of a 16-bit address, and would provide top 16 bits for the bus, while the lower 14-bits would come from the original address. That already gives you 30 bits for 1 GiB of addressable physical memory (and having 4 banks available at the same time instead of just 2 is way more comfortable) and nothing stops you from adding yet another 4 16-bit registers BANK0_TOP–BANK3_TOP, to serve as even higher 16 bits of the total address — that'd give you 16+16+14 = 46 bit of physical address (64 TiB) which is only slightly less than what x64 used to give you for many years (48 bits, 256 TiB).

I was trying to get a grasp on what would be pratical.

Even 4MB would take you hours to load from floppies with a 6502.

Terabytes with a 68000 would also be impractical.

> Even 4MB would take you hours to load from floppies with a 6502.

Depends on your clock. Also, you could use some dedicated hardware, like a DMA controller e.g. 8257, or 8237. From 8257's datasheet:

    Speed

    The 8257 uses four clock cycles to transfer byte of
    data. No cycles are lost in the master to master transfer
    maximizing bus efficiency. 2MHz clock input will
    allow the 8257 to transfer at rate of 500K bytes/second.

and I recall 8237 could do even better, if wired and programmed properly.

Hard drivers were available for the 6502. They were expensive ($10k for a 10MB drive as I recall prices came down a lot, but never affordable in the 1980s)

Processing terabytes with a single CPU was impractical, but you could in theory connect it.

I know someone who - in the 1990s had 5MB connected to his Atari. He had two different expansions, and used all the memory for a RAM disk, as a result his BBS was the most responsive remote system I've ever used - including ssh to the server under my desk (open question, was it really or is this nostalgia?).

The SN74LS610 family chips were specifically designed to do bank-switching memory management like this for 8-bit micros.

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