do you have a reference to exact / realistic scaling laws for the leakage currents as function of capacitor/dielectric dimensions and access transistor dimensions?

using 4 (or 2^N) voltage levels stores 2 (or N) bits, so we can afford to make the structures larger

why would this approach make sense for NAND flash but not DRAM?

Can you back that up with anything about semi-recent nodes? The voltages are so fragile that I'm not convinced you would actually save space once you adjust the design to handle more levels.