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Processors I mostly write firmware for have little cache at all.

I think cache friendly code also tends to be reason about friendly and debugger friendly. None of that is remotely premature optimization.

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> I think cache friendly code also tends to be reason about friendly and debugger friendly.

Not sure what examples you have in mind, but the very first things I think of when I hear cache friendly code are cache-blocking and cache-oblivious algorithms, which are quite the opposite of that. See also B-trees vs. binary search trees, etc.

I usually start with simpler things like paying attention to locality of reference and adjusting data so that it takes up less space in memory.

Even CPUs like the ARM cores have caches, usually 16K, occasionally 32K, and even larger L2 caches (512K).

Well, MCUs tend to have a buffer for execute in place from flash, but often they just have SRAM as main memory which can be accessed with a fixed latency and there is not much point in having a cache.

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