I think the on-chip bus interconnect and ALU are probably going to have some finite width, though. Above that number of bits in an operation, your instructions will get slower. Maybe that's what you have in mind, and you just want to abstract that away?
But I'm thinking more about having multiple logical CPUs, ALUs, or ports working on a single giant register. I think SIMD wastes a lot of hardware.
Example: radix sort needs to calculate a prefix sum. As the sum accumulates, it requires more bits, so the bit length should be adjustable. On x86, you can cast an array of bytes to a uint64_t and calculate eight prefix sums with a single multiplication. But eventually, you run into SWAR lane overflow problems. Ask an AI what this means and how the code works.
We need a CPU designed to handle lane overflow and dynamically adapt bit lengths, so at the start we do more parallel sums with less bits, and as the sum accumulate we increase the bit length gradually. This is just a simple use case. We could store more prefix sums as a periodic sum more deltas.
Besides a lower clock frequency, such a CPU would also have a power consumption, due to a greater total capacitance of the internal nodes.
The number of problems whose solution could be accelerated by such a structure is too low to make it worthwhile.
The latest SIMD instruction sets have a lot of instructions that handle the entire SIMD registers as bit strings, with which many clever algorithms can be implemented, so there is not a lot more that could be done by explicitly partitioning the register file into registers of arbitrary length.
For instance AMD Zen 6 has just introduced a so-called bit-matrix multiplication and bit reversal instruction set extension, which will also be available in future Intel CPUs.
Despite their name of "bit matrix multiplication" which does not suggest much, those instructions (which use either OR reduction or XOR reduction) can implement a great number of bit manipulation techniques, by choosing some appropriate bit string constants for some of the operands (which will mask parts of arbitrary lengths of the bit strings that are combined).
In general, even with the older instruction sets, you can use the SIMD registers as if they would be the concatenation of an arbitrary number of registers of arbitrary lengths.
The only difference from your desired CPU is that you must intercalate in any algorithm many register masking and register copying instructions, which would not be necessary in your desired CPU, because it would remember the current register set configuration with its number of registers and their lengths, until you change it again.
The addition of all the extra instructions needed to simulate a CPU with registers of arbitrary lengths could be done by a compiler or interpreter designed for this.
You'd essentially have a 1 bit processor with a cache that translated groups of bits to whatever memory access width was. CPUs already fill cache lines with transfers wider than registers, so the theory is there.
There's always a sweet spot for bang-for-buck on any tunable size like that. I doubt it is at 1-bit unless you can figure out how to do cache coherency with a few million cores.