> I believe the answer in this case is you latch the signal, and use a local copy.
So the latch is local to both, and therefore not using a signal from another module?
So the latch is local to both, and therefore not using a signal from another module?
sub proc {
my $latch = @_[0];
}
I can see the sourcing issue when trying to fan out too much from a single module, but I don't see any issue doing a high speed interconnect between them as long as you're intelligent about where the modules are going to be placed in regards to chip I/O. i.e. don't have a high speed serdes unit on one bank try and directly talk to a bank on the other side of a chip.
It is a placement/distance problem. Sometimes one module needs to talk to a module on the other side of the chip, and there's no two ways about it. In that case, when you clock it fast enough, you need to break the path across cycles.
edit: It looks like BUF is indeed the Xilinx primitive for a buffer, so no. Definitely not what I meant.
Half-cocked Example:
module test ( a, clk );
input a; input clk;
wire a; wire clk;
reg flop;
always @ (posedge clk)
begin
flop = a;
end
(... useful things ...)
endmodule