Umm, you took "at a ridiculously higher level of efficiency" out of my quote in order to call it silly? C'mon man.
If you've ever diligently crunched numbers on FPGA versus GPU monthly electricity costs at scale, I don't think you'd be capable of saying power efficiency is a strawman. If the idealistic efficient-resource-usage aspect is not convincing enough for you, we are talking millions and millions of dollars here (actually more). Look at Amazon GPU numbers and get back to me. We have detailed breakdowns of price comparisons that have been worked out in depth using the same algorithm. This is nothing like swapping out lightbulbs, that's an actual absurd and uninformed statement that can be verified and quantified as such.
And I do mention both IP blocks (even in quotes as you do) and how SoC's CPU-PL communication is much faster from being same-chip-integrated, hours before you did, so I'm not sure what you mean.
I'm also not getting why you use hard IP blocks as an argument that FPGAs are getting less flexible. They are helping to advance FPGA accessibility and flexibility a ton. Why do you think they're there? The development time savings are huge and the testing and optimization is by nature better.
The 7000 series has pretty heavy options, you can get a lot PL all your own on them. We've been specifically talking about an ARM+PL SoC, are you trying to say that an FPGA like a Virtex or Kintex is somehow not a "blank slate"? You want no standardization of any kind? The lack of that is a huge problem, and it's getting solutions.