Comment by cottonseed | Hacker News Reader

Comment by cottonseed | Hacker News Reader

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Based on my own design attempts, I think two things are holding back open source hardware design: (1) assembling and reflowing complex boards with parts in small, modern packages (0402 or 0201, QFN, fine-pitch BGAs) and (2) modern CAD features like length matching, differential-pair and multi routing and impedance matching: all the things you'd need to design a fast, wide DRAM interface, for example. (I know some off these features are available in free packages, but IMHO they're just not there yet.) These would open up the kind of designs that are currently only available to elite designers with Altium, things like the RaspberryPi, BBB or bunnie's Novena.

I built my own oven and had reasonable luck with two-sided boards with small packages (e.g. 0402) and large 1mm pitch BGAs, but I haven't been able to consistently reflow QFNs. However, it is expensive, time consuming, not buying in bulk kills you, and for complex boards with expensive parts, yield becomes a significant cost factor. I'll be interested to see what their costs are like. A service like this could be transformational.

FCC certification are also a roadblock of sorts for product development.

In theory, I should do testing for verification and or "declaration of conformity" for any run over 5 devices where I have a clock over 1.705 MHz for a battery-only device or over 9 kHz (yes, KILO-Hertz) for a digital device that plugs in, even to recharge batteries.

UL (or equivalent) testing/listing isn't required by law, but represents additional possible expenses if you want to sell to consumers.

It's already pretty daunting, tech-wise, to make the leap from "I have an idea" to "works on my bench on protoboard" to "works on my custom-designed PCB", but at least the out-of-pocket costs and risks are low there.

It's a much greater leap, cost-wise, to get the FCC paperwork in order, even for "unintentional radiators", to say nothing of trying to get a BTLE or wifi device certified.

BTLE and WiFi are getting a bit easier thankfully. I know the TI CC3000 doesn't require intentional emitter testing if the recommended design is followed which saves a _lot_ of money and time. [0]

Agreed that FCC unintentional emitter testing can be a pain, however, unless you're doing something very fancy it's not that hard to achieve, and it's not super expensive if you just need a low frequency unintentional testing.

I'm not a lawyer, but I think you can self declare as well for unintentional emitters, just if you get caught the penalties are much stricter than if you can prove you went through a lab.

[0] http://processors.wiki.ti.com/index.php/CC3000_Product_Certi...

Any idea on the cost for unintentional radiator testing (assuming a clean first-time pass)? I was assuming "4 figures and up"

Edit (after the first two replies below): I'm assuming a slow-clock device, say 20 MHz or less, as that's the limit of my PCB design skills anyway...

I've run a few products through FCC and CE testing, all including motor drivers (noisy) and USB ports (computer peripheral requirements for CE), running on multiple power supplies. Each failed a few tests at least a few times, typical price from start to finish from the testing facility (Austin, TX) was an average of $16k/device from first test to passing report. Not including our costs for travel or re-work.

Depends on a lot of factors: how big (reputable) the company doing the testing is, how big your device is, what voltages your devices runs on, what frequencies are on the board, number of I/O, number of configurations to test (to explain the last part, say your device can either run off USB or ethernet, you'll probably need to test both).

For something simple (clocks less than 200mhz), usually half a day of testing will cost between 1k and 2k I think. However, take these numbers with a grain of salt.

EDIT: they can also help you track down leaks and pass through testing the first time as well (i.e. say you're leaking tons of RF through a badly shielded ethernet port. They can track it down, and will have copper tape so you can test to see if a simple patch will fix it, which if the testing is much more expensive might be an acceptable step to add to your assembly procedure vs. doing a respin of the board).

Our rule of thumb is 30k per product for all tests/rework/retests.

And never assume a clean first-time pass.

So there's a question. How do you reimagine certification testing to cut the cost 10x.

I don't know. There's no doubt a big entrenched market of providers with negative incentive to do that, and I'm not even sure that I see a lot of benefit to the FCC to change the process.

If I was a government employee, I'd probably think it was right and proper to better protect Americans from stray radio interference from slipshod products than to reduce the one-time NRE charges to bring those products to market. It's not that I'm accusing them of shallow-mindedness, just that they have a perspective that the current process is working pretty well. (My perspective of trying to do a production run of 250 or 500 units of something is entirely different, but I can't make a compelling argument that "fixes" my problem without imagining that I might be introducing other, worse-on-balance problems.)

I should state up front I know nothing about the certification process. I agree, there is a lot of benefit to having a working system, even if it means barrier to entry is high. It sounds from your comment like most of the cost is due to the regulatory structure, and not from the testing end, is that right? I'd love to see a cost breakdown of doing a certification. Someone else quoted $250-500/hr for testing. What goes in to that? Testing equipment? Facility build out? Testing technicians?

You're totally right. Obviously, I've never gotten that far along.

QFNs and most reflows are tricky as well, since it requires you to also design the board properly to reflow correctly. For example, if the QFN has a large ground pad in the middle, putting unmasked vias in the middle can cause solder to get sucked down to the other side. To the best of my knowledge, there isn't a great handbook that explains all this, since it crosses a bunch of fields (the electrical design says you will want a few vias in the pad to lower impedance, while the manufacturing might say otherwise [0] or will be able to do it no problem).

In regards to memory and more advanced stuff, the beaglebone/raspberry pi/other system on modules are great for the hobbyist and low volume production, since making what is essentially a computer can be very difficult. It might work on the first spin, but hard to spot issues might occur if the power / grounding isn't good enough, or if there are noise or other signal integrity issues.

[0] http://i.screamingcircuits.com/docs/Via_In_Pad_Guidelines.pd...

> QFNs and most reflows are tricky as well

I've now manually soldered two dozen or so 0.5mm pitch QFN chips without a single failure. To be honest, I'm somewhat surprised myself. I'm using the footprint recommended by the manufacturer, NXP, which has small vias on the edges of the center pad. Since the center pad is VSS, at least one via would be required anyway.

My process is quite simple:

1) I use a soldering iron to tin all the pads except the large one in the center.

2) I apply no clean flux to the freshly tinned pads. If I wouldn't be too lazy to make a stencil I could probably skip these two steps.

3) I apply a blob of solder paste to the center pad.

4) I place the chip.

5) I reflow the whole board with a hot air soldering station. After the solder has melted, I tap the center of the chip to make sure all the pads on the chip have made contact with the pads on the board.

I actually prefer QFNs over QFPs because on QFPs it's really easy to get solder bridges - easy to fix, but more finicky than preparing QFNs in the first place.

I realise this doesn't really apply to manufacturing, but automated manufacturing already has the processes to deal with QFNs.

Thanks! This is super useful. I had a QFN solder failure on one of my last boards. I mistakenly tented the center vias on the bottom, forgot to clear them before reflow, and it seems hot gas escaped, popping the chip off! But it left perfectly tinned pads. I will try your method out.

You reflow the whole board with a hot air station? I've been using an oven. How big a board can you do that way?

> You reflow the whole board with a hot air station? I've been using an oven. How big a board can you do that way?

Yep. It's not really by choice, but because I have limited space. That being said, I like being able to watch the process and to correct minor issues like a 'tombstone' passive, so I think I'd prefer a hot plate over an oven.

My SMD boards are small, the largest one by length is 7 cm and the largest one by area is 25 sq cm. You could definitely do larger ones, but you'd probably get significant temperature gradients - bad for manufacturing, probably ok for prototyping and one-offs.

cottonseed, Chris from Worthington Assembly here.

We've actually reflowed proto boards here with a hot air station. The trick is to get the whole board warm first and then target the gun (or pencil) at the joints. You can use a hair dryer to get the whole board warm and then use the hot air gun to quickly reflow each joint. It's pretty fast and works well.

If you bump the pads like you mentioned with a little solder, you can then flatten the joints very carefully with a flat piece of metal (but end of a small screwdriver or something similar) and then apply a little flux, and then warm the whole board and reflow as mentioned before. Works like a charm!

Hi tcas, Chris from Worthington Assembly here.

We found that when we switched to our super fancy high end reflow oven (that's literally 15 feet long) all those sorts of issues kind of went away. Stencil design has a lot to do with it, believe it or not. Too much paste on the center pad and the QFN just floats up and the joints never get connected. So yeah, if CircuitHub just has a footprint for QFN's that's known to work, you can eliminate a lot of that type of research.

I believe that. Even for 0.5mm QFPs, trying to do a stencil at home controlling the amount of solder paste is very difficult. Almost every attempt I've tried leads to at least a few bridges (easy to fix, but still annoying). With the professional machines you guys have it's probably much more reliable even with not so great stencils.

Do you end up doing a final DFM as well for most submitted stencil files?

Yeah, every stencil file gets thoroughly reviewed. We reduce aperture sizes for fine pitch components, "window pane" large apertures, round-rects on BGA's, all that kind of stuff. If you choose a CircuitHub approved footprint, all that kind of stuff will be taken care of automatically.

Using high-end machines makes life a lot easier too because we have a controlled snap off speed and angle as well as consistent squeegee pressure and paste bead height. You wouldn't believe how many factors go into getting a good stencil print.

Andrew, co-founder @ https://circuithub.com here.

Thanks for the support. I agree completely, really simple stuff is 'quite' well catered for already. Ultimately if your board is really basic and you only need one or two you can do it at home.

The problem is if you want to do something cutting edge or even mid-range it get's really expensive/complex. We're hoping to help with that.

Best wishes, and I hope you are a roaring success!

It's hard to know which is the best option, build a brand new EDA tool and provide this service, or stand on the shoulders of giants in the past. CircuitHub has decided to go the route of allowing you to use your EDA of choice. Right now they support Altium, Eagle, and KiCAD.

Reflow is tough. Getting the profile right so as not to damage components is a real pain without very expensive equipment.

I think it's incredibly important that we get a new FOSS EDA tool with a focus on modularity and usability. I have a really hard time using KiCad because it's so clunky compared to Eagle. The UI for Eagle is better, and the design flow is much easier (for me).

My dream EDA tool is a highly extensible, scriptable, and modular core performing stuff like routing, impedance matching, DRC, etc. and then have that wrapped by a nice Eagle-like UI.

Hi wyager, I'm Chris Denney by the way, CTO for Worthington Assembly

Couldn't agree more. I really think it's going to happen. The EE hobbyist movement is really only in its infancy. The more people that jump on this and get excited about it, the more people will invest their time in FOSS projects like you described. It's only a matter of time.

I agree, and Eagle is utter crap compared to Altium. If the project isn't aiming to eat Altium's lunch, it isn't going to get where it needs to be. And you'd want to have relentless focus on usability. I've followed the KiCad development a bit, but I wasn't inspired. I'd love to work on such a project. I just don't know how to fund it.

I wonder, if the goal was to build a hacker friendly PCB tool: written in python[1], easy to develop for(via extensions), open etc.

What would be the amount of work needed to get to a basic version ? could that be supported by a kickstarter ?

If it could, maybe the rest of the way to altium can be built incrementally ?

[1]there's boldport(https://bitbucket.org/boldport/pcbmode) a python pcb tool , might be a good start

Using Inkscape as a router? Good lord. I don't think that is a suitable starting part.

The right starting point is probably (1) a good choice of implementation tools (I've been sketching out some ideas. I'm thinking C++11 and Qt with python as the scripting language), (2) cannibalizing as much of the existing functionality from other efforts possible: KiCad, gEDA, etc. and (3) then focusing on useability and advanced functionality.

The question is, why not contribute to KiCad or gEDA? That might be the right answer. If they don't collapse under their own complexity (would gcc have gotten to llvm given enough time?), they'll get to Altium eventually. I think the key is to focus on software architecture that enhances productivity. In my experience, that's the only way for a small effort to compete with big, well-funded teams like Altium.

>I'm thinking C++11 and Qt with python as the scripting language

I was thinking it would be cool to do it in pure python, or if that ended up not being fast enough, something like Rust/Python. If we're doing an entirely new codebase, might as well do it right from the start!

OK, you don't like inkscape. but why rule out python? it's faster to code than c++ and more important, it will be far easier to get code contributors(and probably kickstarter support ).

I like Inkscape fine. I use it often to make diagrams in papers. I just don't think it's good for designing PCBs.

I said I totally agree that python should be the scripting engine.

Usually the scripting part is relatively small, i believe.

How much percent of writing such a tool would be in python ?

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