As I mentioned in my other comment Verilog and VHDL are "concurrent by default" since that's how hardware works anyway.

If you want to experiment with them you don't need an FPGA, you can just start with a simulator such as Icarus Verilog[1] and a waveform viewer like gtkwave[2] and get a feel of the language. There are a bunch of tutorials on the net.

[1] http://iverilog.icarus.com/ [2] http://gtkwave.sourceforge.net/

It's a "well-used language" in academic contexts, but probably not exactly an answer to your question ;) Anyways, in OZ[1] you can just add thread <x> end around code x, and it's concurrent. It will wait for all bindings to be resolved before continuing.

It's a pretty cool language with a lot of paradigms one can easily try out.

[1] http://en.wikipedia.org/wiki/Oz_%28programming_language%29#D...

Haskell's Par monad gives you a nice eDSL that lets you lay out your data dependencies and have things evaluated in parallel

http://hackage.haskell.org/package/monad-par-0.3.4.6/docs/Co...

Is Labview concurrent by default?