Take a look at Chisel (http://chisel.eecs.berkeley.edu)... they call it a "Hardware Construction Language" instead of a HDL, as you describe how the hardware works in chisel code, which is just a Scala embedded language. It is then able to generate FPGA or VLSI optimized verilog, and a C++ cycle accurate simulator. I have been using it for the past ~9 months designing a new chip.