edit: even if they just opened up the bitfile format. I believe it's a similar situation as GPU instructions sets though: managers saying "no because patents".
[0] https://github.com/cseed/arachne-pnr
Does it support user constraints on relative placement (and routing)? Self-timed logic, such as NULL Convention Logic [1], doesn't fit well with the synchronous FPGA paradigm, but can be implement on those if the feedback loops are tightly controlled [2]. I'd like to play with that :)
[1] http://en.wikipedia.org/wiki/Asynchronous_circuit
http://www.amazon.com/Designing-Asynchronous-Circuits-Convention-Synthesis/dp/1598299816
[2] http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=543867...For their lower end chips (All the Spartan series, the larger of the 6 series are still quite useful) they straight up announced an end of development on the main toolchain (ISE) with no plans for support on their newer one.
For example, if intel wanted, it could have built a decent FPGA, probably in a reasonable time(there were startups that built decent fpga's).
But building good fpga software ? that it couldn't do, first because it's really hard and second because you need tens of thousands of designs from your customers to run on this in ordered to make good software. That's not something acquirable.
OSS development has proven to be a useful tool as part of greater business models.
As for android - Again it was a strategic necessity for Google, since it needed that distribution point for it's huge ad business. Operating systems are a winner takes all business and the most effective, lowest risk strategy to get there was open sourcing, even though it's kind of a loss leader. And even with only partially open-sourcing android , Google is at constant risk of losing control of android.
The situation in FPGA is different - if altera opens the tool, xilinx and other companies will probably use it , and we'll probably see multiple companies compete on the business.
Here is a link that explains the process: http://curtis.io/others-work/open-tooling-for-fpgas