For a very modern take, [shameless plug] the Mill CPU instruction encoding talk is very entertaining: http://millcomputing.com/topic/instruction-encoding/
(Mill team)
A good example is the Motorola 56K DSP family. Instructions are 24 bit wide (24 bit wide memory!). They come in a few formats, which can be broken down into two major types: complex instruction, or simple instruction plus up to 2 memory moves and address updates.
It's basically designed around performing a single-cycle 24x24->56b multiple-accumulate with two memory reads and address increments, with zero loop overhead. The rest of the ISA really, really suffers for it :) But it's impressive when it's doing exactly what it was designed to do! It's a great example of a domain-specific ISA.
Also worth noting that in 56K, there is no score-boarding or other dependency tracking to automatically insert pipeline bubbles. That's the job of the hand-writer/assembler/compiler. If you get it wrong, it simply does something undefined. It's "fun" when this happen.
IA64 had wide "bundles" for superscalar issue, but it explicitly avoided exposing the individual instructions as "ports" and instead had a more flexible setup where, really, the bundles contained "just a bunch of independent instructions". There architecture assumed they'd all be issued in parallel (so there were rules about dependencies between instructions in a bundle), but made no promises about whether they actually could be, or even whether or not more than one bundle could be issued simultaneously.