VLIW processors with dynamic configuration of the opcode instruction group has a lot of potential in the future, in my opinion. E.g. 128 or 256 bit "opcode groups" with variable-size opcodes, using their own temporary registers, even custom programable opcodes for ad-hoc opcode compression, etc.

The failure of the Itanium because of cheap x86 chips doing "macro-op" execution, more efficiently than the Itanium explicit VLIW, is the other side of the same coin: no matter if explicit or implicit, the way to increase single-thread IPC (instruction per clock) rate is doing more in parallel and hiding execution latency. So, explicit, or as hidden abstraction, VLIW-esque execution seems to be unavoidable.