Marcuss2

Look up what some Chinese LLMs are doing, e.g. mixing some attention mechanism with linear attention layers. Mamba2 layers, Gated Delta Net (2), Kimi Delta Attention and recent Raon Delta Attention (Gated Delta Net 2 + improvement from Kimi Delta Attention)

You are likely to find kernels for Gated Delta Net 2 as Nvidia had a paper on that.

Very little in terms of the layers they use. Calling it now, they are using global layers everywhere, making the model basically unusable due to high KV Cache use.

How would it compare to current state of the art tested state space layers like Kimi Delta Attention?

When it released, it cost $595 (back then, not in today's money), considering the price dropped to just $229 the following year, that was not a good buy when it came out.

Replace all of the engineers with open weight models. And add GLM 5.3 Flash as a builder. I am interested how will they fare.

It is a shorthand for "IMAFD" for RV64.

There is something wrong about this.

> The Planner, Reviewer and Tester agents were assigned the same configuration in every run: claude-opus-4.8 via claude-code, only the Builder configuration was dynamic in the team setup. So, the results read as the difference between builders. That's a SWE in a team.

Yet they show the total cost. Making the comparison irrelevant. Most of the cost is going to be in there with model that expensive.

Also, they show open weight models in `opencode` (I have reservations about it, but fine) and `pi`, in it's most basic config (who actually uses it that way with models this capable?).

Show me actual comparison, from my experience, the planner, reviewer and tester should be different models from different families.

I know the RPCS3 (PS3 emulator) encountered some differences in a floating point instruction where Intel and AMD had different precision, causing de-synchronizations in LittleBigPlanet multiplayer.

Could be down to this.

CH32V003 has RV32EC core, for RV64, yes, there is no point.

For example x86_64 has v1, v2, v3 and v4 baselines, this tells you which instructions they support (e.g. v4 has AVX-512, v3 has AVX2, etc.).

RISC-V RVA22 and RVA23 aren't too different in this regard. Each one prescribes which extensions must be supported by the processor. I saw RV64GC mentioned, this is just a shortening of RV64IMAFDC, so I for baseline instructions, M for multiplication and division, A for atomic, F for floating point, D for double precision floating point and C for compressed instructions.

You can have a baseline E profile instead of I (less registers, some other features stripped), but I don't think we will ever see manufactured RV64E core, trough RV32EC cores exist.