SuperscalarMeme

Okay I think I can clarify this: Electrons trapped in the gate (when storing a 0) come from the substrate. The substrate is connected to ground, and the “lost” electrons are replenished. So yes, net chip weight grows when 0s are written.

However, weight relative to what? All 0s on a chip will be heavier (the heaviest). All 1s would be the lightest. 50/50 1s and 0s would be the middle, which is where I’d expect generic “data” to fall.

So glad someone else also knew about this connection :) Details about Denver are pretty minimal, but this talk at Stanford is one of the most detailed I’ve been able to find for those interested. It’s fascinating stuff with lots of similarities to how Transmeta operated: https://youtu.be/oEuXA0_9feM?si=WXuBDzCXMM4_5YhA

This is a pretty disappointing article with some very questionable examples.

The Imagination Technology example in particular is poor since they were a supplier of intellectual property, not physical goods. So Apple’s usage of them as a supplier had limited bearing on the firm’s other customers or lack thereof. Similarly, the ban of Apple Watches over IP theft has nothing to do with the supply chain issues that the authors attempted to outline.

The thesis is also all over the place. The title indicates the problem is semiconductors, but then lots of the arguments have to do with suppliers outside of semiconductors. If Apple’s reliance on TSMC is the big problem, then why isn’t even mentioned that TSMC is the only competitive fab on cutting edge nodes?

Lastly, the overarching theme is severely misguided. All of these supply chain dealings are as old as semiconductors themselves. When the industry moved towards targeting consumer electronics in the 70s, semiconductor manufacturing moved out of the US long before Apple was relevant. And if Apple weren’t a powerhouse of consumer electronics today, other companies would be doing the same things. It’s just part of the nature of trying to manufacture and sell mass market electronics.

I'll give you an alternate take: the compute power available to EDA software has been roughly scaling at the same rate as transistors on a die. So the complexity of the problem relative to compute power available has remained somewhat constant. So standard cell design remains an efficient method of reducing complexity of the problems EDA tools have to solve.

Not to mention that in-house silicon is all about economies of scale, this is even more of a puzzling move

Performance is agnostic of ISA. Apple's custom designed cores do indeed have a massive performance/Watt advantage over x86 based designs and happen to be using ARM. However, it's not impossible for an x86 CPU to be designed in a similar way. It does, however, get more difficult to do so due to x86's variable length instruction encoding, to which ARM does not have.

That's because you're locked into the x86 paradigm. Look at the leaps and bounds Apple is making with performance/Watt by moving away from x86. This is the cost of legacy.

While I agree the issue is most certainly real, I feel that Apple Silicon is the scapegoat. Computing platforms need to evolve in order to progress, and sometimes the burden lies on developers to keep up. I think this is more of a story about legacy software compatibility and lack of open source solutions.

And I bet you physicists argue that transistors are just abstractions of semiconductors

I don't think anyone suggests using C as an alternative for microarchitecture classes. C still remains one of the best ways to access hardware relative to other software languages. No language is "how computers work" unless you're writing Verilog, but C is the closest to the metal relative to other software paradigms while still being more convenient than assembly.

Radix-4 modified Booth encoding to reduce the number of partial products and then a sort of modified Wallace tree using 4:2 compressors (or some sort of 3:2 & 4:2 compressor combination based on technology node). There is another type of multiplier sometimes used for maximum performance: unlike Wallace trees where you go through steps of tree reduction, the "Three Dimensional Method" looks at each output bit and generates the fastest possible tree from the partial product matrix. The problem with this method (besides area) is that the wiring and layout of cells is highly irregular. However, now that we are in the age of automated tools, this type of design is more feasible. Paper here: https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/p...

If you're interested, this paper from Synopsys has some neat information about datapath synthesis: https://guest.iis.ee.ethz.ch/~zimmi/publications/datapath_sy...