adrian_b

Even in single-threaded performance, where Vera is much better than in multi-threaded performance, it is inferior to Zen 6.

See e.g.:

https://chipsandcheese.com/p/amds-zen-6-family-feeding-the-b...

Take also into account that the SPEC benchmark does not show the significantly greater performance that can be obtained on Zen 6 with programs optimized for AVX-512. With such programs, the advantage over Vera would be much greater.

Vera seems to have outstanding performance only for the narrow applications for which it is intended, AI training, inference and agentic work.

It is not clear how much of the great performance demonstrated by Vera in those applications is due to the hardware and how much is due to well tuned and matched to it NVIDIA software.

It is very likely that the Vera Olympus cores have a poor performance per die area, which is why they have put only this relatively small number of cores per socket.

The Olympus cores seem to be a greatly enhanced version of the Arm Cortex-X925 cores used in the previous NVIDIA products. Cortex-X925 already had excellent IPC, but very poor performance per die area in comparison with cores like Cortex-X4/Neoverse V3 (which is used in the best Arm-based server CPUs, e.g. Graviton5 and Cobalt 200).

Thus Cortex-X925 was unsuitable for a throughput-oriented CPU, and NVIDIA Olympus seems to be the same kind of core, i.e. a core that is useful in a server only if the server contains other components, i.e. GPUs, which do all the high throughput work, and the CPU only orchestrates the work of those components, without having to do much work itself.

The important new information that I got from this is that AMD Zen 6 supports FRED (Flexible Return and Event Delivery), which was introduced first in Intel Panther Lake, at the beginning of this year.

FRED is a great improvement over the extremely inefficient mechanisms for handling interrupts, exceptions and system calls of x86-64, which had been constrained by inheriting most of their features from Intel 8086 and 80286, from more than a half of century ago.

FRED should decrease the overhead caused by the operating system for x86-64 CPUs.

OK, I agree with what you say.

The main reason while the majority of big aquatic animals are eating other animals, while the majority of the big terrestrial animals are eating plants, is the disparity in size between big animals and most aquatic primary producers, which requires at least one intermediate layer of small animals, who gather efficiently the small algae, packaging the nutrients and energy into bigger bodies, which can be gathered efficiently by the big animals.

The multicellular algae have bodies with a poor content of nutrients, because unlike terrestrial plants they do not need to store large reserves of nutrients in body parts like seeds or roots modified for storage, reserves that would be needed sometime in the future, after finding a place to germinate or after an unfavorable season passes. The stems of multicellular algae typically have only the purpose to anchor them to the bottom, to avoid being swept away by currents, so they do not need to contain much edible substance.

So only a few animals, e.g. sea urchins and some snails or chitons and few fish, have developed the special adaptations required to graze multicellular algae, like adequate teeth, because the reward for such an adaptation is not great and the places with abundant multicellular algae are typically restricted to regions close to shores.

Such a CPU is not difficult to design, but the problem is that for the majority of the applications it would be much slower than a traditional CPU, by having a much lower clock frequency, caused by the additional delays through a great number of multiplexers and buffers that would be needed in such a CPU (even the multiplexers that are not implemented with physical gates, but e.g. with tri-state buffers driving common bit lines, introduce extra delays due to driving greater capacitances).

Besides a lower clock frequency, such a CPU would also have a power consumption, due to a greater total capacitance of the internal nodes.

The number of problems whose solution could be accelerated by such a structure is too low to make it worthwhile.

The latest SIMD instruction sets have a lot of instructions that handle the entire SIMD registers as bit strings, with which many clever algorithms can be implemented, so there is not a lot more that could be done by explicitly partitioning the register file into registers of arbitrary length.

For instance AMD Zen 6 has just introduced a so-called bit-matrix multiplication and bit reversal instruction set extension, which will also be available in future Intel CPUs.

Despite their name of "bit matrix multiplication" which does not suggest much, those instructions (which use either OR reduction or XOR reduction) can implement a great number of bit manipulation techniques, by choosing some appropriate bit string constants for some of the operands (which will mask parts of arbitrary lengths of the bit strings that are combined).

In general, even with the older instruction sets, you can use the SIMD registers as if they would be the concatenation of an arbitrary number of registers of arbitrary lengths.

The only difference from your desired CPU is that you must intercalate in any algorithm many register masking and register copying instructions, which would not be necessary in your desired CPU, because it would remember the current register set configuration with its number of registers and their lengths, until you change it again.

The addition of all the extra instructions needed to simulate a CPU with registers of arbitrary lengths could be done by a compiler or interpreter designed for this.

Your quotation is taken out of context, so it has become completely meaningless, but the original text is not so bad as your weird quotation implies.

It is true that the author failed to express himself very clearly, but what he says is that the ancients did not use an abstract unknown denoted by an arbitrary symbol like "x", but they used instead of it the length of some line segment, instead of the squared value of the unknown, the area of some square constructed on that segment, instead of the cubed value of the unknown, the volume of a cube constructed on that segment, transforming thus an abstract algebra problem into a concrete geometry problem, which then they solved.

While that excerpt may not be the best example of mathematical writing, the only conclusion that I can take from it is not that the book must be bad, it might be good, but that the book is written at a very elementary level, so it should be good for children or at most teenagers, but it does not seem to provide any information or idea that would be unfamiliar to someone already experienced in mathematics.

As a child, I have read many books of "popular" mathematics, some of which have made a lasting impression, and perhaps this book is as good as those, taking into account other texts written by Terence Tao, which I have read. Thus the book might be good for a child/teenager who likes mathematics.

Set theory and logic stay below numbers, but they do not belong to quantitative reasoning.

By definition, quantities, either discrete or continuous, as already classified by Aristotle, are the properties that can be expressed by numeric values, as a result of counting for discrete quantities, or as a result of measuring for continuous quantities.

Properties that are not quantities, but which can be compared, to determine which is greater or less, or if they are equal, are qualities (also by definition; there are also properties that can neither be expressed by a number nor compared, so they are neither quantities nor qualities, e.g. the properties of belonging to a certain subset or of having a certain name).

The simplest numbers, i.e. cardinal numbers a.k.a. natural numbers, are equivalence classes of sets, so indeed the theory of numbers is built upon that of sets (a.k.a. multitudes in older language), but this does not contradict in any way the title from the book, because quantitative reasoning refers to only a part of mathematics, not to all of it.

In medieval education, the subjects of learning were partitioned into 3 trivial sciences, which were those that do not need quantitative reasoning, which were grammar, logic and rhetoric, plus 4 mathematical sciences, which were those that require quantitative reasoning, which were arithmetic, geometry, music (i.e. harmony) and astronomy.

Therefore the original meaning of the word "mathematics" referred to the sciences that need quantitative reasoning, while logic and set theory were outside "mathematics" (at that time the primitive form of set theory was included in "logic", i.e. the concepts of set operations and of logic quantifiers).

Much later, towards the end of 19th century, due to their importance for describing mathematics in a rigorous way, mathematical logic and set theory became included in "mathematics".

Humans have learned how to handle big numbers only very recently, not much before the invention of writing and the Bronze Age (the "Bronze" age happened only several thousands years later after the first use of agriculture and after the first use of metals like lead, copper and gold).

On the other hand, small numbers are perceived directly by the senses and recognized, not only by humans, but also by many animals.

The reason for the existence of OoO is that the latency of a memory read is much greater than the executions of tons of instructions.

The only algorithms that do not care about memory latency are the digital signal processing algorithms and the like (which include things like video/audio compression and decompression), where there is a continuous stream of incoming data, which must be processed. When you have a continuous stream of input data, you do not need a von Neumann architecture. The execution units could be organized in a systolic array or the like, through which data flows continuously.

Otherwise, whenever you have to read a previously unused memory location from an address that is not predictable by the hardware prefetcher, you must pay the latency penalty.

There are only 2 ways to hide the memory latency, by doing something else while you must wait the arrival of data. You can either execute instructions taken from elsewhere from the current thread, which is OoO and which requires a lot of complex hardware to find which instructions may be executed, or you can use either fine-grained multi-threading or simultaneous multi-threading, where either the programmer or the compiler have taken care to prepare a lot of independent concurrent threads, so that the hardware may execute any instructions from a thread that is not the current one, without having to search and analyze the instructions, to find their dependencies at run-time.

Because this is much easier for programmers and for compilers, OoO is preferred for CPUs. Where the cost per core must be minimized, FGMT or SMT with a very large number of threads is preferred, like in GPUs.

In the parent article it is said that they will not use OoO, but nothing is said about multi-threading. If neither OoO nor FGMT/SMT are used, the result is a special-purpose processor, not a general-purpose processor, i.e. a processor whose use is restricted to DSP-like algorithms, because otherwise its execution units would stay idle almost all the time.

I have browsed briefly through the documentation of the programming language mentioned in the announcement, but it does not appear to have many features relevant for concurrent programming, not even at the level of the Occam language, which was used for Transputers.

The only unusual feature that I see, is a Fork/Drop thing, which works exactly like reference counts, except that instead of passing references to an object, copies to that object are passed, which is an optimization that may be useful in a concurrent program, but it is something that can be done by a compiler, without being visible in the programming language.

Most small fish eat small crustaceans and other small animals, not algae.

Most phytoplankton, i.e. unicellular algae, is eaten by zooplankton, i.e. mostly by small crustaceans, like copepods.

The fish that eat other animals vastly outnumber the fish that eat algae or aquatic plants.

In open water environments, the kinds of bigger animals, i.e. fish, cephalopods, chaetognaths, cnidarians, ctenophores are almost all predators who, unless they eat each other, they are eating zooplankton that consists mostly of small crustaceans and of planktonic larvae of the animals that live on the bottom.

The corresponding research paper:

https://www.pnas.org/doi/10.1073/pnas.2512066123

Where I live in Europe, a much simpler and better system is used.

No app, no account. I just send an SMS to a certain number, with a code for the kind of ticket that I want to buy, i.e. for a certain bus line or for all lines and the duration of validity.

The money is taken from the credit that I have at my phone company.

None of the problems described in the parent article can happen.

The single-threaded results of the Apple cores are excellent, but the multi-threaded results per socket of a Zen 6 absolutely wipe out any Apple CPU.

The Apple CPUs may be great for a personal computer, but they are not competitive with a server CPU.

Moreover, the SPEC floating-point results are not really representative for the floating-point performance of Zen 5 and Zen 6 that can be reached with optimized AVX-512 programs, which is much greater.

They are unlikely to share circuits with the multipliers, but the 2 of the 6 execution units that include multipliers must be identical, to simplify layout, and the PDEP/PEXT circuits are allocated to these 2 units, like the multipliers.

Besides interrobang, Unicode includes all 4 possible sequences of 2 "?" and "!".

  203C;DOUBLE EXCLAMATION MARK;Po;0;ON;<compat> 0021 0021;;;;N;;;;;
  203D;INTERROBANG;Po;0;ON;;;;;N;;;;;
  2047;DOUBLE QUESTION MARK;Po;0;ON;<compat> 003F 003F;;;;N;;;;;
  2048;QUESTION EXCLAMATION MARK;Po;0;ON;<compat> 003F 0021;;;;N;;;;;
  2049;EXCLAMATION QUESTION MARK;Po;0;ON;<compat> 0021 003F;;;;N;;;;;

AFAIK, links to LWN pages are intentionally always visible to non-subscribers.

In any case, I am not a subscriber and I see it.

Vacuum tubes have huge conduction losses, i.e. the voltage drop on them is very high at high electric currents.

This is why for high-power switching they were quickly replaced by gas-filled tubes, long before WWII, e.g. with thyratrons (General Electric) and ignitrons (Westinghouse Electric).

Semiconductor devices have much lower conduction losses than even gas-filled tubes.

While conduction losses are much less a problem with semiconductor switches, many of the semiconductor switches have high switching losses, which limit their use to low switching frequencies.

Silicon carbide devices have lower switching losses than the older semiconductor devices, and gallium nitride have even lower switching losses than SiC devices, so both enable great increases in switching frequencies, which has many benefits.

As a bonus, in the future (when SiC crystals with a better quality will be available) silicon carbide devices will enable the production of high-voltage switches that require much fewer devices connected in series to reach working voltages of hundreds of kilovolt, or even of a few megavolt.

Nowadays, thermionic vacuum tubes or thyratrons remain sometime competitive in pulse switching applications, but only for very high voltages, i.e. above 50 kV. Even for such applications they have a too short lifetime, and there are better semiconductor alternatives, except that this market is too niche, so the big semiconductor device manufacturers do not bother to make such devices, which sometimes forces the use of obsolete vacuum tubes or thyratrons.

Only for the generation and amplification of electromagnetic waves in the microwave frequency range and at very high power, special vacuum tubes may remain preferable to semiconductor devices (e.g. the magnetrons of microwave ovens or the traveling-wave tubes still used in many satellites).

See my other comment above.

While this is not the principal reason for using bigger wafers, bigger wafers reduce the cost of large-area devices more than they reduce the cost of small-area devices.

As you say, the main reason for using a wafer with a double area is to double the number of transistors that can be made on a wafer, reducing their fabrication cost.

Nonetheless, the reduction in fabrication cost is greater for large-area devices, for 2 reasons.

One is that on bigger wafers less area is wasted at the periphery, where in many places a full die does not fit inside the circle, so an area corresponding with a fraction of a die remains unused. The amount of such wasted area grows quickly with the size of the die.

The second reason is that the dies that are close to the wafer edge, even if they fit inside they have worse yields than the dies that are far from the edge. Again, the proportion of such dies with worse yields increases with the die size and it is lower for bigger wafers.

For now, SiC MOSFETs remain more expensive than silicon IGBTs, even if the difference is today much smaller than a few years ago.

So at any new design, one must ponder whether to use the better SiC MOSFETs or the cheaper silicon IGBTs.

Even if they are more expensive, SiC MOSFETs ensure economies elsewhere, i.e. they enable a higher energy efficiency, which reduces the operational costs for the end user, and also the use of cheaper devices in other parts of the system, which can compensate the higher cost of the SiC devices.

So now any price reduction of the SiC devices is welcome, expanding the range of products for which they will be chosen, thus their market share. The price reduction from using wafers with a double area can be very substantial, not only due to producing a double number of devices with a not much greater cost, but also by improving the yields for large-area devices, because usually the chips that are located close to the edge of the wafer have worse yields.

There already are many recent electric vehicles that use SiC MOSFETs, inclusively from Tesla and this is a market that grows quickly and SiC MOSFETs are a critical component for it, by enabling much better efficiency, size and weight of the electronics, in comparison with the old IGBTs.

I am pretty certain that the new EV chargers that can charge a vehicle in less than 10 minutes, or even in only 5 minutes, by working at voltages of up to 1 kV and currents of up to 1 kA, are made with silicon carbide MOSFET modules and it would have been difficult to make them in the past, when only IGBTs were available.

Even now, after so many bicycles, none of them overlaps correctly the elements according to their 3D positions, so it is still very easy to distinguish the drawings done by an LLM from those done by any competent human.

Free preprint at:

https://arxiv.org/abs/2508.08238

As a child, I made a few such gliders from balsa pieces.

However, a drone must carry some useful load and it would be much heavier than such a light glider, so it would lose altitude quickly while gliding.

Moreover, even a drone that is not intended to go far away, which could reach a nearby destination if launched from a big height or by towing, would still need a battery, some motors and control electronics to control the direction of flight, which would also increase its weight.

A drone that would be able to go very far by gliding would need a lot of sensors and very sophisticated control to take advantage of the air currents in order to avoid losing quickly the altitude and crashing down.

An ordinary drone with flapping wings could glide only for very short time intervals, after which it would have to use powered flight to recover its altitude. Even so, its control would not be easy for avoiding the risk of flight instabilities at the transitions between wing-flapping and gliding.

Fixed wings drones are much more efficient for big and heavy drones.

Their efficiency advantage drops quickly for diminishing sizes and weights.

That is why big birds use gliding whenever they can, but small birds and insects use almost only wing-powered flight.

Screw propellers are pretty much equivalent with wings whose rotation angle is not limited so they can rotate continuously around the body instead of having to reverse periodically the direction of rotation and the attack angles.

Because they did not use electric motors.

Now SiC MOSFETs are the most efficient devices for the power converters used in electric vehicles, where DC voltages of 800 V or 1000 V are used in the latest models, which require, respectively, 1200 V or 1400 V SiC MOSFETs.

GaN HEMTs (high-electron-mobility transistors) are the most efficient devices for the power supplies that are fed from mains electricity, where 650 V GaN devices are used for the universal power supplies, which must accept up to 240 V AC on input.

There is an overlap between SiC and GaN at rated voltages between 600 V and 750 V, but at lower voltages than that only GaN devices are used and at higher voltages than that only SiC devices are used.

Even at 650 V where there are available both GaN and SiC devices, there is little direct competition between them. For such voltages, SiC devices are used for controlling greater powers, where also the power dissipated by the device is great enough to require a big package that enables efficient cooling, while the pure GaN devices (i.e. not the hybrid silicon-GaN cascode transistors) are available only in small surface mounted packages, which enable much higher switching frequencies, but at lower output powers, because it is more difficult to cool them well enough.

For now, the SiC devices are only unipolar devices, i.e. MOSFETs and Schottky diodes. But in the future, when SiC crystals with fewer defects will become available, there will also be SiC bipolar devices, i.e. thyristors and IGBTs. The bipolar devices will be available for much greater powers than the current devices, while also being much faster than the silicon bipolar devices. On GaN, bipolar devices are not possible, so GaN will always be used only for higher switching frequencies, but lower output powers than SiC.

Silicon carbide MOSFETs are the best devices for the SOTA electric vehicles and also for their chargers, which work at 800 V (where 1200 V SiC MOSFETs are used) or at 1000 V (where 1400 V SiC MOSFETs are used).

The Akkadians used cuneiforms much like Japanese use kanji (Chinese characters).

This means that the Akkadians could read a sign either with an approximation of how Sumerians had pronounced it or with the pronunciation of an Akkadian word that was a translation of the meaning of the original Sumerian word. Some signs did not correspond to the syllables that were pronounced, but they specified a class of things to which the word to which they were attached belonged.

Like in many other writing systems, the most ancient cuneiform signs were ideograms, which symbolized various things, like emojis now. Because at that time they had no phonetic meaning, we do not know which was the language of the writers, i.e. if it was Sumerian or some other language that may have been spoken in those places before Sumerian.

However, it is impossible to have a complete writing systems only with ideograms, where "complete" means that it can be used to write anything that you can communicate by speech.

So many centuries later, some of the signs that were used initially to designate a thing began to be used for any other thing that was pronounced in the same way, and eventually most signs were used to write syllables and the cuneiform writing system became a complete writing system. At the time when this transition from ideograms to phonograms happened, the language of the writers was Sumerian and the writing system became a mixture of syllabic signs and determinative signs.

As I mentioned above, after the Akkadians began to use the cuneiform signs they had their way to pronounce them. Because, like for Japanese texts, there are many alternatives for pronouncing the cuneiform signs, the correct deciphering of such texts is not easy.

The things described at that link cannot be fixed in any simple way.

There it is said that Ginux does not implement mutual exclusion in the right way for a multiprocessor.

To implement this correctly and in a way that ensures high performance even on CPUs with hundreds of cores is one of the most difficult parts of an operating system kernel, much more difficult than just implementing the system call interfaces, to enable a user program to run.

Other point is that Ginux is vulnerable to some races caused by interrupts, which is again something difficult to get right in an operating system kernel, unless you copy exactly the corresponding code from the Linux kernel.

From a practical point of view, Ginux cannot be called anything else except a toy operating system kernel, at the level that previously could have been a home project for one student at an OSes course.

Of course, despite being a toy, Ginux is an impressive accomplishment by being good enough to run an unmodified Linux user program, and its implementation with an LLM has required at least an order of magnitude less time than a human student would have needed.

Still, there is a very long way from a demo like this to seeing an LLM that can generate autonomously a real operating system kernel, without further interaction with a human after the initial specification.

It should be remembered that the main purpose of an operating system kernel is not implementing the API of the system calls used by the user programs, which is the trivial part of its functions. The kernel is the manager of the shared resources of a computer system, like CPU time, memory, peripherals, which allocates them to user programs and ensures that their usage is maximally efficient and that the user processes cannot use the shared resources otherwise than as decided by the kernel. This is something that Ginux has not accomplished at all, based on the description from the link provided above.

USA, which is famous for engaging in several smuggling operations, like the Iran-Contra affair or the many cases when CIA was allegedly involved in drug trafficking.

I doubt that. Android has advantages only for consumer devices.

Anything with Cortex-A35/Cortex-A32/Cortex-A34 may be useful only for some embedded devices which run Linux. They are much slower than even the chips with Cortex-A53 that were used in the cheapest smartphones from more than a decade ago.

In fact anything with Cortex-A35/Cortex-A32/Cortex-A34 is too slow to be useful for anything, because much faster chips with Cortex-A55 are available at much lower prices from vendors like Rockchip and several others. Even some much better SBCs with Intel Atom CPUs are available for a price 4 times lower.

A board with Cortex-A55, PCIe, USB 3 and with everything else that the author of the TFA desired can be bought for a 10 times lower price than that ST development system.

I am using a lot of ST development boards, but they are various versions of the cheap Nucleo boards, which have an excellent price/performance ratio.

Their more expensive boards and more expensive microcontrollers that can run Linux are not competitive in price and features with the boards using cheaper N-series Intel CPUs or with the boards using various Cortex-A55, Cortex-A520, Cortex-A76, Cortex-A78 or Cortex-A720 that are available from Chinese vendors.

Renesas uses them, but the Renesas MCUs are quite expensive, even if they seem to be the best.

So if you are willing to pay a high price, which might not be worthwhile, it is not difficult to find MCUs or development systems with Cortex-M85.

As I have already mentioned in another comment, Cortex-A35 is not the replacement for Cortex-A7, but for the smaller and slower Cortex-A5. Because of that, Cortex-A35 is slower at the same clock frequency than Cortex-A7.

The successor of Cortex-A7 was Cortex-A53, which was followed by Cortex-A55, then by Cortex-A510, and so on, until the current Arm C1-Nano.

The line of Cortex-A5 and Cortex-A35, which includes Cortex-A32 and Cortex-A34, can be considered dead, because using so slow CPUs instead of the best Cortex-M or Cortex-R cores (like Cortex-M85 and Cortex-R82) does not make sense.