bobmcnamara

Combo wireless keyboard with touchpad.

Inten never bought it from Ovonyx, so how could they sell it?

Intel and micron licensed the 3D XPoint nonvolatile memory cell from Ovshinsky/Ovonyx, then bled them dry by delaying royalties, eventually stopping payment altogether until they went under.

Eventually someone in the know bought the husk of Ovonyx and sued Intel.

Intel pirated Optane and bailed when they got caught, seemed unrelated to AI, just Intel being Intel.

My 2025 Toyota has two clocks, one from Toyota, one from Android auto.

The Toyota one requires selling your driving data to insurance companies.to update the tzoffset based on location.

And so two clocks on the dashboard are off this week until I can remember where the dst adjustment is in the settings.

That usually works well enough for risc code.

As a massage, I wish there was a flag to set a minimum branch target size. If all the branch targets for a switch are the same size then you can often turn the jump table into a multiply-accumulate, or sometimes even a shift and add.

It comes up in emulators and VMs, and indeed those are often tool generated.

The Kohl's of AI

The Gerber standard just doesn't describe a PCB, just the shape of the layers. I would've sworn there was old dead Gerber, GerberX(the one you want), and then some newer ones that are unreliably implemented across programs.

You almost always need an NC drill.

You have to add a separate GerbJob to describe what the board is made of.

IPC-2581 is the future.

Good riddance to the compatibly hellhole of 30 different flavors of Gerber/Gerberx/NCdrill

EDIT: haven't even mentioned everyone's different goofball CSV BOMs

The real KV cache was inside of us the whole time.

A web accessible PHP runtime is, in fact, a giant security vulnerability and always had been.

Still waiting for high speed rail

Whoa, one of these is right up the road from a cannibal murder.

Small world.

I hope things are better now, but there used to be 1.5 poor choices:

1) use uncached DMA buffers 2) manage cache host CPU coherency by hand. 3) hope you only ran on hardware cache coherent architectures

And the kernel didn't give you everything you needed to do #2.

Just reading a USB2 480p webcam on a raspberry pi burned half the CPU kernel memcpying pixels from uncached DMA rx buffer to cacheable buffer. At least the camera is a linear copy, but the USB packets are relatively small.

Plus it's the same ram cartel players since the early 2000s.

It's also a huge propaganda opportunity to influence the distribution of groupthink.

Costs dropping opens you up to competition on price.

Nice try Philipp Mainländer!

Web and database servers were the target maybe?

I ran Minecraft server on mine.

> but the C for them is its own little world playing by its own rules, separate from C used everywhere else.

Sadly, this isn't unique to micros...

> All relevant platforms

Don't make me tap the sign: the majority of processors running C are weird little dirtbag chips of 16 bits or less sprinkled by the dozen.

Plus char could be signed or unsigned!

Oh geeze I went from an UltraSPARC III to a T1 and performance tanked.

Turns out my use case was not large numbers of parallel integer only threads.

> There is no monopoly on computer memory.

Never has been, but what makes you think the major players won't collude to keep prices high?

Intel and IBM have already done this almost this with their wide eDRAM caches.

The advantage in going wide is transferring cache lines rapidly, not the CPU bus interface.

Or on DRAM on die compute

> Before becoming two parts they probably were part of the same parent protobrain tissue.

Article says they weren't.

Trying to keep the rest of GH online?

Creeps presumably.