carry_bit

It's basically a 16-bit machine with PAE; 32-bit with PAE runs into similar issues if you want an object larger than 4GB.

There's a whole lot of C and C++ software out there, and Fil-C makes it memory safe, frequently with minimal work.

Problem? That's the intended result.

Just make them internal and use [InternalsVisibleTo] on the assembly.

It would just be a useful reminder of that fact. Remember: you're trying to sell voting to someone who doesn't normally vote. It's easier to sell it as being a one-off thing versus sell them on voting in all future elections.

The country is in good enough shape that they can go back to not caring if it's a Democrat or Republican in the White House.

> Do you guys got not feel shame if a person with that character and that track record runs your country?

The Donald Trump that your media reports on isn't the real Donald Trump, or at the very least the one his supporters see.

Example: Trump talks to a group of people who normally don't vote, and asks them to make an exception and vote this time, noting that this will be the last time he runs, and so they won't need to vote for him again. The media then takes "you won't need to vote for me again" out of context and uses it to claim that Trump will end elections in the US. People who only listen to the media see one thing, and his supporters (who are aware of the context) see another.

GDP is a flawed measure, and that's especially true when you look at the 70% figure in detail. For details see https://treeofwoe.substack.com/p/gross-domestic-fraud

A closely related technique for debugging optimization passes is that of "optimization fuel". Each rewrite decreases the fuel by one, and when the fuel is gone no more rewrites happen. You can then perform binary search on the optimization fuel to find a specific rewrite instance that breaks things.

The state-of-the-art in refcounting[1] greatly improves the barrier situation over a naïve implementation: no read barrier, and the write barrier only uses atomics when mutating an (apparently) unmodified field in an old generation object.

[1] https://dl.acm.org/doi/pdf/10.1145/3519939.3523440

State-of-the-art referencing counting does not require atomics on every single object; see for example https://dl.acm.org/doi/pdf/10.1145/3519939.3523440

The language is a term rewriting language. https://reference.wolfram.com/language/tutorial/Evaluation.h... covers most of the evaluation process. The documentation for functions lists out the different forms they expect.

Lisp-style macros are actually difficult to write because of the infinite evaluation of the language. I was able to write a quasiquote package for myself to help with that that though.

It's been a few years at this point; everything I was able to find towards that effect was enabled from what I remember.

If they're able to deliver what's in the email I'll be picking one up.

Hopefully you would actually be able to get a full speed transfer between the Ethernet ports; I had to go back to the factory firmware on my router in order to take full advantage of my 1 gigabit Internet connection.

Reminds me of componentized jQuery. It appears this has you have to once again apply DOM patches manually; hopefully you implement that correctly every place you update the state.

In these parts, if you're fortunate enough to have a heated garage, you're keeping it just above freezing to keep the costs down. Still quite a difference between that and how warm you want your car to be.

Performance Improvement Program

Unused code paths were once used or it was thought that they would be used. If you don't know if something is used, it's safest to assume it is being used or is there for some reason (Chesterton's Fence). If it's being used, you need to maintain it lest there be a regression.

You'd have multiple communities existing in the same space interacting akin to normal and dark matter. The reputation of one can spill over and affect the others.

You can technically do it, but I don't it being worth the hassle.

If the future model is going to be anything, I suspect it'll be pay-to-join networks where it is primarily the users that are moderated instead of the content.

Communities are echo chambers with a range of allowable discourse. Moderators serve the important function of keeping that range anchored so the community stays cohesive over time.

AIUI, the full peer is Datomic; the RPC server is just a full peer that exposes the API over http and is mainly intended to be used with clients that don't run on the JVM (and so can't run Datomic itself in-process).

Nuclear is dense, comes with months worth of storage built-in, and lets smaller countries be self-sufficient for a while without having to rely on other countries.

Insects are not a good idea, and you might not be aware just how efficient the chicken is: https://www.youtube.com/watch?v=L8e0pU92dmI

Yep, they have that now.

There's a darwin-arm64 asset for https://github.com/YosysHQ/oss-cad-suite-build/releases at least. Installation is just 4 steps (see the readme). It just worked for me on Windows and Linux at least.

I've been learning a lot from the https://zipcpu.com/ blog lately, and I'm just starting to play around with formal verification after reading all of the recommendations for that from the blog.

SpinalHDL has been very nice to use so far instead of Verilog: https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html It even has simulation and formal verification workflows built in. In the simulation you can wiggle the bits on your ports using Scala, so you can code an emulation of any peripheral or the like that you want and have your design use it. (You can also do the same thing using C++ if you use Verilator directly instead.)

You can code a bridge between a serial port in your simulated design and a TCP port, and then write a second program to bridge a real serial port to a TCP port the same way. You can then write tools that connect to the TCP port and then use those same tools against both your simulated design and your design in hardware.

I'm watching this video about TL-Verilog, and the part starting here shows how powerful it is for that kind of thing: https://youtu.be/hQ6HhOBHKy0?t=2048

In short, you can define generic reusable flow constructs like stall and backpressure pipelines. You can then instantiate them and slot in your logic, and signals will be automatically pulled through the different stages and pipelines as needed. The example at this part of the video shows then how adding something can be a two line change when it would be hundreds of lines if you were working at the RTL level: https://youtu.be/hQ6HhOBHKy0?t=2581

Nice that you support multi-cycle memory instead of essentially using a big register file like https://nandgame.com/ uses.

I recently came across https://makerchip.com/, and the TL-Verilog language it supports looks useful for when you want to make a pipelined design later.

The value of values: https://github.com/matthiasn/talk-transcripts/blob/master/Hi...

Having values and having your program phrased as transformations of values makes for straight forward, easily tested code. Provide inputs, assert outputs.

Think of it as manual testing where your work is captured so it can be ran later in an automated fashion. There are many problems where verifying the answer is easier than coming up with the answer.

Asserting formatted output can also be really useful. A picture might be worth a thousand words, but when it comes to tests it can save you a thousand asserts. Writing those thousand asserts separately also would be so tedious that in practice you'd probably not write them all, leaving part of your output uncovered by tests.

When I wrote a LALR parser generator for fun, I added some code to print out a nicely formatted parsing table with debugging information. Besides being useful for debugging, it let me write simple yet powerful tests: I would feed the generator a grammar and then assert on the formatted parsing table. That made it easy to verify that I was asserting the right thing, and let me assert everything in one go.