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Why refactor the code?: less repetition, clearer intent, easier to change timing/logic by editing a table instead of code paths.

Feedback welcome—especially ideas to extend it.

(This post is part of Resorte, a Spanish magazine (comics, hobbies, technical notes) inspired by Argentina’s legendary Lúpin. If you read Spanish, check it out.)

All the sources for the designs and testbenches were tested on Vivado and are available at GitHub. For the generic implementations I used unconstrained ports, which gives much simpler and compact code than using generic parameters.

The implementation of the round-robin arbiter uses a very clever and (again) compact algorithm.

Honey and lemon juice, mildly hot (put water in a pot, and the honey and lemon juice in a smaller glass inside the pot, stir until it is liquid and mildly hot).

Grandma recipe, works for me. Not a medical advice

For me, one option is to be able to learn processors in depth. You want to understand how one works? You can always emulate it in SW, but on an FPGA you can make them interact with the real world in real time and probe them at the same time, with ready made signal analyzers that the vendors provide, and/or by making your own tools.

Another option, do you want to see by yourself how caching improves code performance? You can make that on an FPGA also.

I have done some time ago a very nice course which is called From Nand to Tetris, that teaches how to go all the way from gates to a processor. My plan for the near future is to implement the NAND2Tetris processor on a Basys 3 board, and make some of the examples I mentioned (like, probing internal registers using HW tools, or seeing by yourself how a cache improves performance). I hope to make some of these things available on my site. I am the OP, but just in case, my website is https://fpgaer.tech

Following Altera acquisition by Intel, and Xilinx acquisition by AMD, perspectives for many FPGA designers were gloom. There was a general feeling that the two biggies would go to a road where the FPGA is only and add-on or coprocessor for CPU workhorses, for applications like Data centers and ML acceleration.

Well, according to these news from Intel, that's not the case. Intle announces new mid-level FPGAs and even new FPGA to compete with Xilinx RFSoCs

Very very nice, but I don't like that the cars are transparent

That's also the first thing I thought when I saw the title

That it why it was so much a joy to buy magazines. Those magazines with their program listings, the adds, the letters. I remember to this day when I was with my girlfriend for a long time typing long listing of POKEs to hear music from the magnificent SID.

If I were you, I would try to reach to the blog poster.

Thanks!

I know it is not directly related to this magazine, but this nostalgia brought back to me the name of my favorite magazine those days: Ahoy!

And of course, who can forget the wonderful adds for the games from Infocom (Zork et al), who would "stick their graphics where the sun don't shine!". They were text based games, and very succesful on those days

No, I haven't. And for your second question, I don't think that the tools I use are obscure or don't get enough attention.

Don't take advice from anyone. Including me.

Hi, I am a professional FPGA designer. I used to be a board designer many years ago, and most of the time I used the tools from Mentor Graphics. Only when I worked for a startup I used Orcad who, compared to Mentor Graphics, was really in another (much lower) league. The differences between Mentor Graphics and Orcad (15 years ago, when I was still a board designer) were many: Processing speed, integration between schematics entry, constraint management and layout tools, etc.

Being a HW digital designer, timing is everything :)

You are welcome!

The problem is nice but the solution proposed at the website is too convoluted. The straight solution is simple. The mid door must say the truth, so left and right doors must lie. Taking these three simple facts into account, the exit is on the right door.

So it was not intercepted by an Alien vessel... :)

For me is one of the loveliest series I have seen

I am a dad of grownup children myself. My daughter is married and my son is getting married soon.

One of their strongest memories is about the songs we would make them hear while traveling around in our car, when cars had CD-ROM players.

Thanks, I might, eventually.

J. Poniachik, BTW, was a mathematician from Uruguay, very active in the field of Recreational Math, having published quite a few magazines and books about this during his life, and also created several puzzles and games that are know worldwide, for example, this one - https://en.wikipedia.org/wiki/Battleship_(puzzle)

About him: https://es.wikipedia.org/wiki/Jaime_Poniachik (also in Spanish - I don't think there is an entry for him in English)

Well, then I would say it was not a good interview. And yes, if you can, go to as many interviews as possible. There is a 'mood' for passing interviews and the more you do, the more you approach them with the right mood.

Difficult to say. I have interviewed lots of people over the years, and have noticed that many people in charge of the interviews barely read the CV in advance.

If you were already invited to an interview, a good interviewer should make most of his impression from you yourself and your answers, and less from the CV. From the applicants side, these days it is common for people to put lots of buzzwords... and when you ask many times you discover that they know not many more than the buzzword name.

So a good interviewer should make a lot from the interview and not from the CV. But then, a lot of other things come into play: Yours and his attitude that day, your 'chemistry', etc. Passing an interview is tough and it is recommended to go as much as you can, since practices makes perfect.

Thanks for your comment. You may have noticed that duty_cycle is indeed an input. Some of the other constants could be indeed input as generics. In general I prefer to use packages, since it makes instantiation simpler, and parameterization can be done by using different packages for each block. Of course generics have advantages of their own.

Direct link to falcon mesa fact sheet: https://newsroom.intel.com/newsroom/wp-content/uploads/sites...

(as posted at reddit by ProgrammableGatorade)

You may be having a confusion between tristate buses and open-collector, or open-drain, drivers

I am the author of the article and it may seem wrong to you but it is the way things unfolded. Once interconnections were faster than the transistors, at the beginning of the 2000's that fact was reverted, now transistors are much faster than interconnection. It is the reason behind many other development, like multi-core devices. Since transistors are faster than interconnections, it is reasonable to make many units working fast than a big unit working slower because of the interconnections.

The tristate buffers were abandoned on the FPGA market, followed by the ASIC market.

I don't know ADA, I have always thought that Verilog is like old C and VHDL like C++. Not that VHDL is object oriented, but is a strong-typed language.

For many years now I have been using mainly Altera and VHDL. Lately I started a new job and returned to Xilinx which I have not used for long. Part of my job is integrating three major IPs, and guess what? One of them is VHDL and two others are Verilog. So yes, sure, you can wrap a Verilog code with VHDL and forget it... but, the Verilog IPs come also with their Verilog testbenches, etc. So for me it will be a bilingual reality for some time to come.

On the last releases of Vivado, Xilins is making a big push for HLS. Personally I have not still had the chance to learn and try it.

Ah OK well I will do in a few days... Don't want to SPAM. Thanks