damageboy

The rules don't apply for reporters outside of Israel, and this was historically been the way that Israeli journos and other bypass the censorship completely.

The author is being pressured (IMO) because the degens feel like they can threaten him (physical proximity)

I can see why systolic arrays come to mind, but this is different. While there are indeed many ALUs connected to each other in a systolic array and in a data-flow chip, data-flow is usually more flexible (at a cost of complexity) and the ALUs can be thought of as residing on some shared fabric.

Systolic arrays often (always?) have a predefined communication pattern and are often used in problems where data that passes through them is also retained in some shape or form.

For NextSilicon, the ALUs are reconfigured and rewired to express the application (or parts of) on the parallel data-flow acclerator.

No real overlap with Cerebras. Have tons of respect for what they do and achieve, but unrelated arch / approach / target-customers.

You can indeed and should assume there is a heavy JIT component to it. At the same time, it is important to note that this is geared for already highly parallel code.

In other words, while the JIT can be applied to all code in principle, the nature of accelerated HW is that it makes sense where embarrassingly parallel workloads are around.

Having said that, NextSilicon != GPU, so different approach to acceleration of said parallel code.

Not really. I work for NextSilicon. It's a data-flow oriented design. We will eventually have more details available that gradually explain this.

Yeah, it's an unfortunate overlap. The Mill-Core in NextSilicon terminology is the software defined "configuration" of the chip so to speak that represents swaths of the application that are deemed worthy of acceleration as expressed on the custom HW.

So really the Mill-Core is in a way the expression of the customer's code. really.

I work in NS. The riscv was the "one more thing" aspect of the "reveal".

The main product/architecture discussed has nothing to do with vector processors or riscv.

It's a new, fundamentally different data-flow processor.

Hopefully we will improve in explaining what we do and why people may want to care.

Then your org is over paying for mediocre HW, at least for servers, arguably also for laptops (Dev machines for sure) At least for the last two years.

Thank you for writing the obvious. Instruction Byte count is the wrong metric here 100%. Instruction Count (given reasonable decoding/timing constraints) is the thing to optimize for and indeed variable length encoding is very bad.

OP from twitter here. I'll take the blame for the click-baity-ness, but I was really shocked and this was in real-time in my defense.

I'm assuming it will get resolved, as the errata suggests by shoving lots of 0x2c segment overrides to re-align those jumps.

The price won't be 0, but will definitely less than the very extreme 20% edge case I stumbled upon.

I'm more "worried" or annoyed by older binaries that will never get updated. But hey... (；⌣̀_⌣́)

Isn't this a whole lot of words for installing traefik with DNS challenge and let it do basically all of the work?

Fault? He is getting free publicity to the point he is even on the front page of HN (not that he care about this specifically). Show me the last time this happened with a French book up for a prize.

Would be interesting to see how xsv compared to miller (https://johnkerl.org/miller/doc/index.html) in terms of perf, this tool comes exactly as I am about to munge 1TB of gzipped csv files.

Unfortunately, the main operation I need is not supported by xsv...

What a load of crap... you just wasted 2gb of address space not of DRAM... You'll "waste" exactly up to the amount of stack each thread uses, rounded up to PAGE_SIZE which is usually 4kb

Let me guess, a nodejs fan?