djf··on FPGAs for fun & hackingAfter a think, ignoring the VHDL syntax,I think the Verilog example has edge sensitive set/reset, whereas the VHDL has level sensitive set/reset? I don't write Verilog mind so I'm guessing a bit...
djf··on FPGAs for fun & hackingAssuming the second one is supposed to be VHDL, there are so many syntax errors that I can't figure out what the OP's intent is...