henrikf

That's very impressive and I'm even more impressed if you can manage to sell tiles at that low price.

PA looks suspiciously similar to SE5004L. I just needed some for my own projects but every distributor is out of stock. I wonder if this is where all of them went?

That's Leela Zero (plays Go instead of Chess). It was good for its time (~2018) but it's quite outdated now. It also uses OpenCL instead of Cuda. I wrote a lot of that code including Winograd convolution routines.

Leela Chess Zero (https://github.com/LeelaChessZero/lc0) has much more optimized Cuda backend targeting modern GPU architectures and it's written by much more knowledgeable people than me. That would be a much better source to learn.

It was from JLCCNC.

There's not much software. PC calculates PLL register values for correct LO and source output frequencies, and transfers them to the FPGA which writes them to the hardware. FPGA accumulates the downconverted samples from the receiver ADCs. Samples are transferred to PC which calculates ratios of the receiver outputs to get uncorrected S-parameters. scikit-rf Python library is used for calibration and plotting.

I have also had issues with motivation. I had a long pause from about 2019 to 2024 where I didn't work on personal electronics projects because I didn't have enough motivation. This and last year however I have been very productive and it's hard to say what exactly changed, just felt like working on them.

It's not on Github, but I do have schematic at the end of the blog post. vna2 is the previous version.

Thanks for the submission. Author here if you have any questions.

No, it needs to be done manually. It wasn't as tedious as it sounds though. Most of the pins are very close in delay already and there were just few traces that I had to adjust a little.

The FPGA manufacturer has characterized all their package pin delays. It's possible to export a csv file with internal delays of the package for each pin from the FPGA design tool. With Xilinx Vivado it's just File -> Export I/O Ports.

I actually didn't use any expensive test equipment, only oscilloscope and multimeter. Even design and simulation software was all open source.

Expensive signal analyzer or spectrum analyzer would have been useful, but they aren't absolutely necessary. It's possible to use the radar itself for many tests and debugging.

I have tried to limit the projects I do on my own to only the equipment that I have home and open source software.

I built it to see if I could. I didn't have any particular use case in mind.

Putting ground planes on top and bottom layers isn't usually done with high speed PCBs because components are there. There would need to be a cutout on the ground plane near every chip. High speed signals really need continuous ground plane and ICs, especially RF ICs, need short access to ground. Second layer is the best layer to minimize the distance from ICs to ground plane.

That's a mistake in the text. You're correct that layers 2 and 5 are ground planes.

What's open sourced here is the design kit. Designed chips need to be sent to IHP to be manufactured.

SiGe isn't also that useful for military radar applications. Compared to SiGe GaN has much greater breakdown voltage which leads to greater output power and better efficiency. It's possible to get 10 to 100 times more output power from GaN chip compared to SiGe. It isn't really possible to make high performance long range radar with just SiGe although it could be used in some parts of it.

This is a very fast BiCMOS process with both MOSFETs and bipolar transistors. Some digital logic can be implemented with MOSFETs but since they are 130 nm it's not very competitive with smaller cutting edge CMOS processes. Bipolar transistors are really the whole point of choosing this process and it's aimed for implementing analog and RF circuits. Bipolar transistors are extremely fast and can be used to make amplifiers operating at >200 GHz. MOSFETs can be used to implement some simple digital blocks for controlling the RF blocks.

I have made several tapeouts with this process and I have very good experiences with it. Compared to other open source PDKs that Google has open sourced previously this one is quite modern and offers very good RF performance.

It doesn't seem quite ready for design yet. Transistor models and stackup are published so schematic level simulation is possible. There is a roadmap chart in the repository (https://github.com/IHP-GmbH/IHP-Open-PDK/blob/main/ihp-sg13g...) and it seems that they are going to offer free MPW runs.

Author seems to be looking to generate a blue noise texture for image sampling. I'm not familiar with them but it seems to be blue noise which also has uniformly distributed values in time domain. Generating white noise in frequency domain and multiplying with a frequency shape mask can generate noise with any frequency distribution, but it does not fill the uniform distributed values in time-domain requirement.

If there are no other requirements than the frequency spectrum then generating the noise in frequency domain works fine.

Even worse than error message is incorrect results. I worked on the OpenCL neural net evaluation backend used in Leela Zero and lc0 Go and chess bots. We had reports of several OpenCL drivers being so broken that they gave incorrect results while appearing to work correctly without giving any error messages. Intel integrated GPUs on Apple were the worst offender and it looks like the drivers are never going to get fixed. Some older AMD cards had similar issues. We had to add a check that GPU NN evaluation matches CPU reference to catch these broken drivers.

If I understand the methodology correctly this study seems to penalize unlimited plans quite a lot. In the linked methodology pdf they specify that the price for 1 GB of data for unlimited plans is calculated by dividing by the average data usage per user but limited plans are divided by the limit.

For example in Finland almost all plans are unlimited and users regularly use a lot of mobile data. Average monthly use is 34 GB and median 6 GB [0]. The cheapest mobile plan I can find is 9.90€/month for unlimited data at 1 Mbit/s [1]. Dividing it by 6 GB median data use gives $1.95 for 1 GB which is close to the their reported minimum price of $1.75. However if this plan was instead marketed with 100 GB monthly cap they would have divided it by 100 GB instead giving a much cheaper price.

[0] https://blog.telegeography.com/finns-lead-the-way-in-mobile-... [1] https://elisa.fi/kauppa/puhelinliittymat

No need to wait for AlphaZero, you can try Leela Chess Zero today. From my experience the network without search has some blind spots, but the tree search is pretty effective in fixing them.

On the same PSLV C38 rocket was Aalto-1, a 3U cubesat that has electrostatic plasmabrake that is a different de-orbiting experiment. It uses 100 m long hair thin wire that is electrically charged and brakes the satellite by interaction with the ionosphere. https://www.electric-sailing.fi/papers/Plasmabrake.pdf

It has an advantage of not needing any propellant and being very light weight but it doesn't work above the ionosphere. It should work for de-orbiting small satellites in LEO. The same principle should be possible to be used as a solar sail for interplanetary travel by interacting with the solar wind.

That's the rumours I was referencing. Deepmind hasn't confirmed anything yet.

Deepmind released three AlphaGo vs. AlphaGo matches last year and around the new year AlphaGo played 60 games against top professionals online winning all of them. There have been rumours about AlphaGo vs. Ke Jie (No. 1 Go player), but nothing has been confirmed yet.